Site: NEC Tsukuba Research Center
Fundamental Research Laboratories
34 Miyukigaoka, Tsukuba
Ibaraki-ken 305, Japan
Tel: 81-298-50-1159; Fax: 56-6139
Date Visited: January 28, 1997
WTEC Attendees: J. Rowell (report author), F. Patten, H. Morishita, R. Ralston
Hosts: Dr. Jun'Ichi Sone, Senior Manager
Dr. Hiroyoshi Rangu, General Manager
Dr. Matsuo Hidaka
Dr. Tsutomu Yoshitake
Dr. Shuichi Tahara, Research Manager

BACKGROUND

In its R&D brochure, NEC states, "The Tsukuba Research Laboratories, a center of NEC's advanced basic research, explore the frontier of basic science, creating new concepts, materials, and devices." One such discovery was of carbon nanotubes. As one university professor that the WTEC panelists met said, "NEC is a very unusual case, exceptional and amazing (in keeping fundamental work)."

NEC also has a most distinguished record in low temperature superconducting electronics. As a participant in the MITI-funded 10 year project, along with Fujitsu, Hitachi and ETL, it advanced the Nb trilayer discovery (Bell Labs, 1982) into a reliable technology. In this project, the NEC focus was on memory circuits, and this emphasis has continued recently. However the group, with its manager Dr. Shuichi Tahara, now has a wider variety of LTS and HTS activities. These were described to us by Dr. Tahara and his colleagues. The Senior Manager of the Advanced Device Research Laboratory, Dr. Jun'Ichi Sone, and the General Manager of the Fundamental Research Laboratories, Dr. Hiroyoshi Rangu (Roy Lang) also joined us for discussions.

R&D ACTIVITIES

Dr. Hidaka first described NEC's work to develop HTS junction technology, using a sampler circuit requiring 5 junctions as an example. The junctions are ramp-type, with PBCO as the barrier. In contrast to most groups in the U.S., which make the ramp by ion milling ex-situ, the NEC approach is to make the ramp in-situ, followed by the PBCO and second YBCO deposition without exposure to the environment. Test patterns of 50 junctions are used to test uniformity, which is noticeably improved by the in-situ process compared to (NEC's) ex-situ one. However, the spreads (1 sigma) of 26% shown to the panel are larger than the best "Big 3" (Conductus, Northrop Grumman, TRW) result in the United States, which was about 12% to 15% at the time of this WTEC visit. In discussion, achievement of a spread of 10% was mentioned. Initially, the junctions were prepared over a ground plane, but the rough surface of this film degraded the junctions. In the recent circuits, the ground plane is added over an insulator covering the junctions. Loss of oxygen (and Tc) from the films of the junction was said to not be a problem. To date, the sample has been tested successfully at low speeds.

Dr. Yoshitake described NEC's work on microwave applications. The interest of the group is in the space applications of filters and in delay lines for ATM switch buffer memories. For satellite communications, power handling of the filters is an issue, and a simple microstrip resonator at 5.7 GHz is being patterned from double-sided YBCO on MgO to test the HTS films' potential in this regard. These resonators are measured in an Nb shield at 4.2 K and have Qs of about 60,000. Significant variations in power handling are observed from film to film, but in common with much of the work in the United States, relating these variations to measured electrical or microstructural properties of the films is proving difficult. The effect of grain size and grain boundary properties are being investigated.

The nonlinear behavior of HTS filters has been investigated by measurements of a 3-pole band-pass filter at 9.5 GHz with a fractional bandwidth of 2%, again using double-sided YBCO made by laser ablation on MgO. The Q was about 10,000 at 55 K. The third order distortion products were measured to 30 dBm and extrapolated to over 60 dBm, but high power measurements have not yet been made.

A different application being investigated is to use coplanar delay lines as buffer memories in ATM switch cells. The 18 cm long lines have only 5 µm spaces between the center and ground conductors, which in the past resulted in shorts due to precipitates in the YBCO film. A change in patterning process was needed to overcome this.

NEC's achievements in building 4 kbit LTS memories are well known (see, for example, IEEE Trans. Electron., E79-C: 1193, 1996). These were reviewed by Dr. Tahara. The memory chip contains 21,000 junctions, 2 µm x 2 µm in size with 1.5 µm interconnect lines, making it by far the most complex active SCE circuit to date (the 10 volt voltage standard has a similar number of junctions). Initially, the flux trapping problem was tackled unsuccessfully by operation in a field of 20 µgauss. However, addition of moats to the circuit improved the bit yield to 99.8% in one case, and the shielding requirements can be relaxed to 1 milligauss.

At about the time of this WTEC panel's visit, the goal had been to shrink the size of the memory cell to 10 µm x 10 µm, which requires 1.3 µm x 1.3 µm junctions, minimum linewidths of 0.5 µm, critical current density of 6 x 103 amps/cm2 with 3 Nb wiring layers. The organization of the chip has also been changed to sixteen 256 bit blocks. Operation of small parts of the chip at 512 MHz has been confirmed. This chip represents a state of the art of Nb technology that is well beyond that of any group in the United States.

The NEC group is also investigating a switching application of LTS technology, funded under FED's hybrid systems project. The aim is to build an interconnection network to improve the performance of multiprocessor systems. In contrast to the crossbar switch of Bedard's project in the United States, a ring-pipelined architecture is being built. Some components of the chip have been tested at >1 GHz, for a total rate of 1.25 Tbits. The chips require about 103 gates and a higher junction current density of 3 x 103 A/cm2 has been used.

The presentations of the technical programs were followed by a lab tour, including viewing (from outside) the class 1,000 fab and class 100 lithography cleanroom. During general discussion back in the conference room, a number of interesting points were made. Roughly 40% of the funding for the LTS and HTS projects comes from the government (MITI, FED). NEC researchers feel that the company is well behind the United States in wireless applications. They have interest from the NEC space systems division in the size and weight reduction potential of SCE. They have no research activities on HTS filters for cellular phone applications.1

Reservations were expressed about the potential of optical switching, and optical transmission and SCE switching were considered more likely. There is a desire to increase the efficiency of HTS funding in the next phases of the ISTEC and FED projects. ISTEC was seen as coordinating the infrastructure of SCE, and it was hoped such activity would continue or increase.


1As the WTEC panel heard during the week (see RCAST and Saitama University site reports), the decision by NTT to end such HTS wireless filter activity seemed to have had a ripple effect in companies that supply equipment to NTT.
Published: August 1998; WTEC Hyper-Librarian