Site: Future Electron Devices Research and Development Association (FED)
Sumitomofudosan Building
8-10-24, Akasaka, Minato-ku
Tokyo 107, Japan
Tel: 813-3423-1621; Fax: 813-3423-1680; E-mail: sup@fed.or.jp
Date Visited: February 3 and 4, 1997
WTEC Attendee: J. Rowell (report author)
Hosts: Mr. Shuku Maeda, Managing Director

BACKGROUND

Following the week of visits organized by WTEC, at the kind invitation of Mr. Maeda, I attended a 1-1/2 day review meeting of the superconductivity program of the Future Electron Devices Research and Development Association (FED). Both Professor Kostya Likharev and I presented talks on the afternoon of February 3.

FED is a foundation established by the Japanese electronics industry in 1981 under the license of MITI. Its main purpose is to promote R&D projects aimed at the development of novel devices useful for future electronic industries, in cooperation with national research institutes and universities, and to disseminate the R&D results to the industrial community. The R&D projects are conducted under contract with the New Energy and Industrial Technology Development Organization (NEDO). Research management is carried out by FED, while R&D is subcontracted to member companies and universities, with research on more basic technologies being carried out by the national institutes.

R&D ACTIVITIES

The subjects of completed FED projects have been superlattice devices, three-dimensional ICs, fortified ICs for extreme conditions, and bioelectronic devices. Ongoing projects are Superconducting Devices (1988-1997) and Quantum Functional Devices.

After the discovery of HTS, MITI funded research into the science of the oxide materials and studies to create new materials at ISTEC, where (as described in the ISTEC visit report) industry sends its members to a central laboratory. In contrast, work on superconducting electronics (SCE) applications was funded in the laboratories of the industry members of FED (and at ETL). So both centralized and distributed "centers" have been used in Japan in response to the excitement generated by HTS. Chapter 8 details the advantages and disadvantages of each style, as this panel sees them. Because the LTS digital project was still ongoing in 1988, the FED Superconducting Device project initially chose the topics of three-terminal devices and studies of HTS film preparation and microfabrication technologies. In the early 1990s, after the end of the LTS program, FED added the topic of Hybrid System Technologies, which supports research at Hitachi, NEC, and two other companies. These were two members of the earlier LTS project that (along with ETL and Fujitsu) developed very good Nb trilayer technology.

The participants in the FED project are Hitachi, Fujitsu, Sumitomo Electric, Sanyo Electric, Oki Electric, Toshiba, NEC, and Mitsubishi Electric. Presentations of the work of each group were made on the second day of the meeting, followed by a small banquet, which allowed very useful informal discussions.

Five of the companies are studying 3-terminal devices, but three of them have added other research topics to broaden the activity. The 3-terminal device studies have been valuable exercises in improving growth techniques for HTS and other oxides (see the Sumitomo site report), but none of the devices seem competitive with silicon, or with voltage state or RSFQ SCE circuits in terms of speed and power dissipation.

Research into HTS devices includes step edge junctions at Hitachi, Ag-doped YBCO flux-flow transistors at Oki, and BKBO bicrystal junctions exhibiting SIS characteristics for mixers (Mitsubishi). The in-situ process for SNS junctions is described in the NEC site report. Dr. Yoshida's group at Toshiba has performed an extremely thorough investigation of transport in PBCO barriers (with Au counterelectrodes to eliminate the effect of shorts) and has addressed the important question of the physics of transport and the proximity effect near the metal-insulator transition. SNS junctions using Co-doped PBCO as the barrier have been used in SQUIDs and simple circuits.

The LTS activity at NEC, with the objective of building an interconnect network for a silicon multiprocessor system, is described in the NEC visit report. At Hitachi, a different switch architecture is being built with the Nb trilayer technology. The goal of the 3-year program (ending March 1998) was to build a 4 x 4, 4-bit SCE packet switch operating at 4 GHz. Arbitration logic has been used to solve packet contention. Achievements include the demonstration of a 2 x 2 Banyan switch at 4 GHz, and the test of a 4 x 4 Batcher sorter at lower speed. The LTS process technology at Hitachi seemed to be a source of some concern to the scientists there.

In other discussions during the WTEC panel's trip, and at FED, the question of funding for the LTS programs after March 1998 frequently arose. It seems clear that MITI will not fund LTS projects (the ISTEC view of LTS, like the view of many in Washington, seems particularly negative), despite the much more advanced state of the technology compared to HTS anywhere in the world. Indeed, the NEC LTS technology appears to be at a level of its own worldwide. It would be a great disappointment to many in the field, including those of us in the United States, if this capability did not continue to advance. Regardless of its commercial potential (or lack thereof, given the need for 5 K cryocoolers), it is the only way to build and test SCE circuits and systems of any interesting level of complexity at present. This view seems to be shared in some quarters in Japan, and it is possible that other sources of support (maybe the Science and Technology Agency, STA) will be found for LTS programs. Whether FED will be involved in such funding after March 1998 was a topic of discussion at the time of this WTEC visit. It seems likely that ISTEC will dominate HTS activities, and perhaps the industry LTS programs will be supported separately. For further discussion of this topic, see Chapter 8 of this report on collaborations.


Published: August 1998; WTEC Hyper-Librarian