Electrotechnical Laboratory (ETL)|
Ministry of International Trade and Industry (MITI)
Ibaraki-ken 305, Japan
|Date Visited:||January 28, 1997|
|WTEC Attendees:||M. Beasley (report author), G. Gamota, M. Nisenoff|
Dr. Koji Kajimura, Deputy Director General|
Dr. Hajime Shimizu, Director, Physics Science Division
Dr. Akira Shoji
Dr. Hiroshi Akoh
Dr. Masao Koyanagi
The Electrotechnical Laboratory (ETL) is the premier government laboratory in Japan working on electronics and is wholly funded by the Ministry of International Trade and Industry (MITI).
The WTEC team was warmly greeted by Dr. Koji Kajimura, Deputy Director General of ETL. He emphasized how ETL was trying to be even more visible internationally and to contribute to the world reservoir of science. He noted that ETL's annual technical report will soon be available on the Internet. ETL has 600 researchers, 100 of whom are working on superconductivity in some manner, including power applications. ETL tries to look ahead on a 5- to 10-year timeframe but recognizes that some things take longer. The lab has been working in the superconductivity field for 30 years.
In response to a question from the WTEC team, Dr. Kajimura explained that ETL will benefit from the increased funding for basic research in Japan in response to Basic Law 135. It will use the money to go deeper (i.e., more support under each researcher) not to broaden or to grow substantially. The management expects to have a large post doctoral program, for example, and was beginning to think through where these postdocs can expect to find employment after leaving ETL.
The discussion then turned to ETL's work in superconductivity. Funding for the superconductivity work, a total of about $6.8 million, comes from various MITI programs:
Note that the MITI contributions listed above do not cover the salaries of the 100 ETL researchers.
Dr. Kajimura then excused himself and the WTEC team heard technical presentations. Hazime Shimizu, Director of Physical Science Division, introduced the speakers.
Akira Shoji outlined the LTS digital program. He described their goal to build by the year 2005 a 3 to 4 GHz Josephson junction (JJ)/CMOS hybrid system with JJ logic at 4 K and CMOS (memory at least) at 77 K. Shoji emphasized the need to put the JJ logic, mux/demux, and semiconductor drivers all on one chip for performance reasons (minimal latency). The CMOS will be 0.1 micron technology, which should run at 1 GHz operating at 77 K. The JJ stack drivers will be used to take the 3 mV JJ signals up to 30 mV in order to drive the CMOS. In response to a question by the WTEC team, Shoji said there were no plans to look at advanced memory concepts and that they would use cold CMOS.
He described ETL's advanced Nb/Al oxide/Nb process. It uses an I-line stepper, ECR etching, and a chemical/mechanical planarization process. The researchers expect this to be adequate for a submicron JJ technology. They are also studying vertically stacked NbCN junctions with MgO tunnel barriers as a route to higher output voltage amplifiers by virtue of the higher superconducting energy gap of NbCN compared with Nb. Shoji showed data from 5-JJ stacks that give a 20 mV output. With STM gap spectroscopy studies they have observed much greater gap uniformity with NbCN compared with NbN.
Shoji then outlined some very aggressive technology goals for the future (by 2003) for LTS and HTS JJ RSFQ: a 105 junction integration level for LTS and a 103 junction integration level for HTS.
Hiroshi Akoh then presented ETL's HTS results. The ETL researchers have taken an all-epitaxial (103) oriented trilayer YBCO/PBCO/YBCO approach. Etching is done with argon ion etch. A gold layer is used to wire up the junctions at this stage. He emphasized the need to have uniform temperature during deposition of the YBCO and described the special substrate holder they have developed to achieve it. He also noted that precise composition control is required in order to avoid precipitates on the surface. Test chips have 175 JJs, with 3 x 3 micron to 50 x 50 micron areas that scale properly with area. IcRn = 0.78 meV at 4.2 K. The Jc spread is 34% for 1 sigma and for RnA is 25%. There is no area dependence of the spreads. The ETL researchers feel that much better control of surface and interface properties will be necessary in order to achieve improved spreads.
Akoh explained that they chose PBCO as the barrier material because it is lattice matched to YBCO and that they plan to explore various dopants in PBCO. They were also studying transport properties of PBCO. They had no imminent plans to study the Tl or Hg families of HTS compounds for applications.
Masao Koyanagi then presented the advance metrology work. For HTS work the ETL researchers use ramp and bicrystal Josephson junctions and are exploring NDT imaging applications. They also have carried out a current standard project and are now looking into X-ray detectors.
Koyanagi also reviewed Kashiwaya's single-crystal HTS STM studies related to the question of zero bias anomalies and the symmetry of the pair wave function in the high temperature superconductors. Ihara then reviewed his interesting work on a low anisotropy Cu 1234 HTS compound.
In response to questions by the WTEC team, the ETL researchers stated that they have some low level interactions with the International Superconductivity Technology Center (ISTEC), e.g., exchange of samples. They are also exploring the possibility of device collaboration in the future, but feel it is essential that they maintain independence in their research. (During the lab tour we also were shown a large database on HTS materials ETL is generating in collaboration with ISTEC which will be available to the general public.) ETL researchers stated that they have no work on high power filters and do not plan to do any. Finally, they stated that there is only a very small two-person effort on cryo-CMOS at ETL. This work is not in the superconductivity section.