TECHNICAL ACTIVITIES OF ISTEC, PHASES 1 AND 2

The emphasis of the first phase of the center was on discovery of new materials and understanding their physical properties. A number of achievements in SCE have been noted in the technical chapters of this report. These include progress in growing large single crystals of YBCO as substrates (Fig. 9.4), the liquid phase epitaxy (LPE) growth of YBCO films (a film growth method that is not used in the United States), investigation of the advantages of alternative 123 compounds, such as NdBCO, exploration of novel types of Josephson junctions, and development of high frequency HTS mixers.


Fig. 9.4. (L) SRL's large single crystal pulling furnace, and (R) a large YBCO single crystal (ISTEC).

The WTEC panel expects that the SCE activities of the SRL will become more prominent in the second phase, which will have three thrusts of a more applied nature: applications of bulk HTS materials, wires, and films. These represent the traditional power and electronics applications in addition to the work on bulk applications such as bearings, levitation, and magnets using trapped flux. Thus, ISTEC will be the only center or consortium anywhere in the world that will attempt to cover the whole range of HTS applications. In the panel's view this will represent a formidable management challenge, both administratively and technically. For example, we know of no scientist who has expert technical knowledge in all these applications who would thereby be qualified to be the Chief Technical Officer or Chief Scientist of such a center. Presumably, the three thrusts will therefore operate as separate groups, each with its own technical leadership. (In the summer of 1997 the WTEC panelists heard that a group of three scientists, experts in SCE in Japan, will act as advisors/managers to the SCE project at SRL.)

The thin film or electronics thrust of Phase 2 will emphasize the development of single flux quantum (SFQ) technology using HTS junctions. This is a complex challenge, in that panelists did not observe in Phase 1 any evidence of emphasis either on device physics or on specific system issues. (However, the three advisors to this program, announced more recently, are experts on these issues.) Further, the present level of HTS junction and circuit process technology does not allow the fabrication of chips of any interesting level of gate count. In the United States, this problem is finessed by developing rapid single flux quantum (RSFQ) technology and building test circuits and subsystems, using LTS chips, usually made in the Hypres foundry (also at Stony Brook, Lincoln Labs, Northrop Grumman, and TRW). It is not clear how SRL will obtain low temperature superconductor (LTS) chips if it plans to follow the same development path, because the LTS process technology exists in a project funded by Japan's Science and Technology Agency (STA). If SRL management waits to design and make RSFQ circuits until after an HTS integrated circuit technology is established, Japan could remain many years behind the United States in RSFQ capabilities.


Published: July 1998; WTEC Hyper-Librarian