In Japan, as in the rest of the world, SFQ circuit technology is the leading candidate for HTS applications. This is a natural choice, given the superior speed and power characteristics of SFQ logic; it is also dictated by the availability of only nonhysteretic HTS Josephson junctions. It seems unlikely that HTS voltage state logic would be used, even if a suitable HTS tunnel junction were successfully fabricated.
Given the choice of SFQ logic, the projected operating temperature is dictated by the need to lower thermal noise to a level consistent with the required bit error rate. This constraint is fully appreciated in Japan, as it is elsewhere in the world. It is now generally agreed that the operating temperature is unlikely to exceed 50 K; hence, there is no driving force to use the highest Tc materials, and all digital HTS work in Japan is focused on YBCO (and to a lesser extent, BSCCO). On the other hand, there is no evidence that there has been in Japan (or elsewhere in the world) a thorough examination of the tradeoffs between bit error rate, operating temperature, superconducting material, and cryocooler technology.1
In keeping with the systematic, long-term point of view prevalent in Japan already noted several times in this report, the Japanese have not tried to select a favored HTS junction technology. All HTS junction approaches familiar in the United States are under study in Japan. There are in addition some approaches being investigated in Japan that are not currently being pursued in the United States. For example, at the International Superconductivity Technology Center (ISTEC) there is work on an in-plane "a/c/a"2 junction and on focused ion beam junctions.
In Japan there is also considerable emphasis on vertical, sandwich-type junctions, as opposed to the in- plane types most common in the United States. This emphasis is motivated by the feeling that in the long run such junctions will permit better interface control and hence better spreads.
For superconducting-normal-superconducting (SNS) junctions, PBCO is the favored barrier material by a wide margin, due to its favorable epitaxial relationship with YBCO. Unlike their U.S. counterparts, Japanese workers have not been discouraged by the disappointing device figures of merit (specifically, low IcRn products) exhibited by YBCO/PBCO/YBCO SNS junctions to date. At the same time, there has been some outstanding work on the physics of PBCO barriers at Toshiba under the FED program, which may eventually make it possible to assess whether or not the performance of current PBCO barriers is intrinsic.
Unquestionably, the Japanese are presently driven by material growth considerations and not by maximizing device figures of merit; therefore, it is not surprising that they have not tried to systematically decrease spreads for specific junction approaches. Correspondingly, they are well behind the narrower spreads achieved by the so-called "Big Three" (TRW, Northrop Grumman, and Conductus) in the United States. Typical spreads (1 sigma) in Japan are 25%, as opposed to 10-12% and continuously decreasing in the United States. Figure 5.2 shows this progress in junction parameter spread and the implication for anticipated circuit size. On the other hand, looking ahead, ETL has a stated goal of an HTS digital integration level of 103 junctions (1 sigma of 8%), and ISTEC has recently announced a goal of 5%. Indeed, as reported by M. Toriihara at the Arlington, VA workshop for this WTEC study, ISTEC is greatly increasing its effort on superconducting electronic materials and devices and has also announced a goal of developing a 5-layer, 1,000-junction circuit technology in the next 5 years (Fig. 3.1, p. 16). These goals set by ETL and ISTEC are aggressive, and if achieved, would open up a much higher (and potentially useful) level of circuit complexity. The ingredients necessary for Japan to make marked progress in HTS digital applications are clearly in place. There may even be some healthy competition present.
Fig. 5.2. U.S. progress in decreasing junction parameter spreads enables digital circuits with increased complexity (courtesy Northrop Grumman).
To date only simple, single-layer HTS digital circuits have been successfully fabricated in Japan. The emphasis clearly has been on basic materials work and on exploration of various junction technologies. Thus, it is not surprising that the United States is further ahead in HTS circuit fabrication.
There also is no evidence of consideration of HTS superconducting transmission lines as on-chip interconnects or multichip modules for cooled semiconducting electronics. By contrast, there continues to be some low-level, long-term interest in this possibility in the United States.
2That is, an a-axis/c-axis/a-axis oriented YBCO.