The differences between the digital electronics activity in Japan now and in 1989 during the original JTEC panel visit are remarkable. Eight years ago LTS digital was predominant; the emphasis decidedly swung to HTS soon after the discovery of the new materials, with one of the several ramifications being that little additional effort has been expended on LTS digital integrated circuits since the end, in 1990, of the 10-year Josephson Computer Project funded by Japan's Ministry of International Trade and Industry (MITI).

Impressive Josephson Computer Results (1980-90) -- A Japanese Domain

The Japanese Josephson Computer Project was a substantial, sustained, and highly productive effort with participation by the Electrotechnical Laboratory (ETL) and the Central Research Laboratories of Fujitsu, Hitachi, and NEC. The accomplishments included

The efforts were only loosely coordinated but resulted in variants of the Nb/Al- Al2O3/Nb tunnel junction, first demonstrated at AT&T Bell Laboratories, being harnessed for complex digital circuits. This MITI project clearly established Japan's leadership in latching digital integrated circuits (ICs). Indeed, a review of the tables within the electronics chapter of the 1989 JTEC report shows several impressive circuit accomplishments. One that was particularly noteworthy was the Fujitsu effort that produced 3000-gate (24,000-junction) microprocessor circuits with 1.5 µm diameter junctions and demonstrated functionality at a 1.1 GHz clock speed. Other examples were somewhat less complex microprocessors at Hitachi and ETL, as well as random access memory (RAM) of 1-4 kbit at ETL, Fujitsu, and NEC. Memories were not fully functional, and typically had several bad cells attributed to photolithographic defects, but access times were as fast as 590 ps. Late in the project, work was initiated at ETL to combine multiple chips into a high-speed package, and at Fujitsu an innovative through-the-Dewar-wall packaging scheme was demonstrated for high-speed operation.

Diminished Digital Innovation in Japan (1990-Present)

Despite the impressive technical results, MITI sponsors were ultimately disappointed that no operational systems resulted from the Josephson Computer Project. Because of this and the enthusiasm associated with the discovery of HTS, the LTS activities in Japan were abruptly scaled back at the conclusion of the project.

Instead, for much of the 1990s, the Future Electron Device (FED) program in Japan emphasized development of novel three-terminal device structures (mostly HTS), with little practical accomplishment of significance for integrated circuit use. (See the FED site visit report in Appendix B.) No structure has yet been invented that can compete with the transistor for general logic and memory use. After initiation of the FED program, NEC and Hitachi later joined the mix of efforts with an emphasis on developing an LTS hybrid Josephson junction (JJ)/CMOS data switch. This particular FED project is described in more detail later in this chapter.

The evolution of the original LTS computer activities is discernible at three laboratories, with some continued effort on NbN junctions at ETL, data switch development at Hitachi and NEC, and refinements in RAM at NEC. Table 5.1 summarizes the status of the NEC memory work. Use of moats to control flux trapping has reduced the defects, and careful attention to the fabrication process has enabled the increase in size to 4 kbit organization and a reduction in critical path access time to below 400 ps. The full memory based on 55 x 55 µm vortex transition cells has not been exercised at high speed, but NEC researchers have proposed a hybrid technology tester for that purpose and hope to be funded to complete the demonstration of the memory. Certainly, even without the tests, no better superconducting memory exists anywhere. But it is also true that such a memory is inadequate in size for most applications. Using a shrink of design rules to submicron features, NEC recently demonstrated an 8.5 x 11.5 µm cell which the researchers project to 1 Mb/cm2 density (IEEE 1997). Still, much effort remains to solve the memory deficiency of superconductive technology.

Table 5.1
Josephson 4 kbit RAM Characteristics


4,096 word x 1 bit

Access time

380 ps

Power dissipation

9.5 mW

Bit yield

99.8% (with moat structures)

Josephson junctions

Nb/Al- AlOx/Nb

Number of junctions

~ 21,000

Critical current density

3,250 A/cm2

Minimum junction size

2 m m x 2 m m

Minimum line width

1.5 m m

Cell size

55 m m x 55 m m

RAM size

4.5 mm x 4.5 mm

Nonlatching Circuit Innovations (1990-present) -- A U.S. Domain

In contrast to the lack of circuit development in Japan and despite the fact that the U.S. community had equally high expectations for HTS digital circuits, there was a trend within many U.S. laboratories to formulate candidate circuit architectures and test them for viability first in LTS form. Interest was especially strong in the potential for much higher speeds in single flux quantum (SFQ) circuits, which also seemed more compatible with the non-latching HTS junction technology.

Substantial innovation in SFQ logic non-latching was a natural outcome of the diversity of U.S. government funding sources. Programs that drove such innovations were (1) the Department of Defense (DOD) University Research Initiative (URI), which fostered circuit innovation at SUNY Stony Brook, the University of Rochester, the University of California at Berkeley, and Stanford University; (2) the Department of Commerce Advanced Technology Program, which united Conductus, the National Institute of Standards and Technology, TRW, U.C. Berkeley, and Stanford in a 10 GHz hybrid data switch development; and (3) DOD, which has funded a variety of analog-to-digital (A/D) converter and data switch efforts in industrial and government laboratories.

In Japan, novel concepts in latching gates are being explored at Nagoya University. Also at Nagoya, Prof. Hayakawa is advancing the view that HTS has many years to mature, and thus LTS (either Nb or NbN) must be exploited for complex circuit demonstrations.

LTS Process Innovations (1990-present) ? A U.S. Domain

The demands placed on LTS fabrication engineers in the United States, through a combination of the need to validate new non-latching circuits (often with high junction current densities) and the continued drive to engineer and demonstrate signal-processing and data-routing circuits of substantial complexity in latching logic, have resulted in the United States regaining the lead in fabrication technology. This lead is reflected in two important dimensions:

  1. A readily accessible commercial foundry at HYPRES is available to supply any IC designer with a rapid prototype of a circuit in Nb-trilayer technology at modest cost. This service has played an important role in the URI initiatives developing rapid single-flux quantum (RSFQ) logic. A broader range of foundry services is provided by TRW, which supports both Nb and NbN technologies. The recent TRW experience has seen the number of NbN chips fabricated increase to approximately equal that for Nb.
  2. Custom/captive fabrication facilities in at least three locations (MIT Lincoln Laboratory, NIST Boulder, and SUNY Stony Brook) are yielding circuits with planarized wiring layers implemented with a chem-mechanical polish identical to that employed in state-of-art silicon foundries. This planarization provides better control of inductances, junction sizes, and contact parasitics, thereby increasing operating margins in the high speed circuits. The process at MIT is, in fact, run in a submicron silicon tool set and thus leverages at modest additional cost the full investment in equipment, which is only made affordable by "excess" capacity within the semiconductor IC market.

No such accessibility for testing circuit innovations or sharing fabrication assets exists in Japan today. This situation may be changing, however, with new collaborations (as distinct from consortia) being planned.

As an aside within the process technology arena, it is worth noting that there are interesting junction explorations in NbN ongoing at ETL, Kansai Applied Research Center (KARC), and Nagoya University. The capabilities of the two countries are similar, but in neither Japan nor in the United States is it clear to what level of circuit complexity can NbN yield fully functional circuits.

New LTS Digital Collaborations in Japan

The U.S. community previously identified data switches as an appropriate application target for LTS (and ultimately HTS) circuits. The Japanese have now selected switching for a collaborative STA-funded project. Non-latching, single-flux-quantum circuits are likely to be the central focus of the activity, with industrial participation by ETL, Fujitsu, Hitachi, ISTEC/SRL, and NEC, and university participation by Japan Women's University, Nagoya University, and the University of Tokyo (RCAST). A possible ingredient in this collaboration could be that NEC provides foundry services, and that would be a significant improvement over the situation at the time of the WTEC team's visit in which university researchers in particular had little access to fabrication facilities.

Another promising collaborative effort is the Ministry of Education's Vortex Electronics Project, part of MOE's program for Scientific Research in Priority Areas. The 3-year, $1.5 million/year project was scheduled to get underway in April 1998 and cover HTS SQUID, HTS Digital and HTS Photonics with the primary emphasis on investigation of vortex dynamics in the junction region. Professor Takeshi Kobayashi of Osaka University's Faculty of Engineering Science leads the group of approximately 30 university and industry scientists.

Ongoing, with a review scheduled for 1998, is the project in Hybrid Systems funded by MITI through FED. The contextual system vision for this program is illustrated in Fig. 5.1.

Fig. 5.1. Josephson hybrid system (FED).

With regard to LTS digital circuits, the switching networks being explored at Hitachi and NEC are particularly relevant. The NEC group has published the low-speed operation of the major building blocks of the ring network as implemented in Nb trilayer technology. Hitachi is pursuing a variant of a crossbar switch, also in trilayer technology. Either would communicate through an ETL-developed (possibly NbN) interface to cold (77 K) CMOS memory. Although no cryo-CMOS activity was described in Japan, ETL conservatively projects that 0.1-micron-gate CMOS would operate at above 1 GHz clock speed.

The U.S. activity in cold CMOS does appear better attuned to these needs. At least one of the small U.S. venture firms, STI, is a partner in a major initiative in accelerating workstations with cold CMOS. Furthermore, the Defense Advanced Research Projects Agency initiative in low-power electronics, which features 0.25 µm CMOS on SOI (silicon on insulator) substrates has demonstrated 1.1 GHz clock rates at 2.5 V bias and is an excellent candidate for insertion into hybridized cryoelectronic subsystems.

Published: July 1998; WTEC Hyper-Librarian