Herb Goronkin
WTEC Panel

The complexity of integrated circuits has increased by miniaturization according to scaling rules that preserve chip speed and power dissipation. It is anticipated that by the year 2005 critical dimensions of 50 nm will be required (e.g., for the 16 Gbit DRAM). At those dimensions, normal scaling of conventional MOSFETs will no longer improve performance at the same rate unless the operating temperature is significantly reduced or drastic new technologies are developed.

The trend in gate length reduction has followed an exponential rule since before 1980 and continues today; following this rule, feature sizes will shrink to about 100 nm by the year 2002. The difficulty arises from the fact that gate oxide thickness scales with the gate length. For example, when the gate length is reduced from 250 nm to 150 nm, the corresponding oxide thickness scales from 4 nm to 3 nm. Such scaling maintains roughly constant power dissipation and chip speed over successive generations. However, when the thickness falls below 2 nm, tunnel current can be greater than the channel current, and the gate will no longer control channel charge. The approximate number of electrons in a 1 Gbit DRAM transistor scales to slightly more than 100 and will reach a value of about 20 in a 4 Gbit transistor. Subsequent generations of transistors that follow the same scaling trend will have current-voltage characteristics that are uniquely different from conventional saturating characteristics today. When the number of electrons is sufficiently small, thermal fluctuations can blur the distinction between on and off states. Post-MOSFET ULSI technology will likely be one in which the basic MOSFET building blocks are replaced by nanoscale devices that exhibit quantum effects. Issues of size and composition control become extremely critical in the case of single-electron devices. In such devices, changes in current with voltage occur in steps rather than continuously. For room temperature operation, the device size must be less than 5 nm for such behavior to become observable and potentially usable. It is not presently clear how such devices will be fabricated. So far, fabrication of room temperature devices has been accomplished using a scanning tunnel microscope tip. Room temperature operation has also been achieved in a polysilicon channel in which quantum size defects embedded in grain boundaries exhibited coulomb blockade effects.

In addition to the requirement for extreme uniformity of composition and thickness in crystalline nanoscale transistors, it will be necessary to control the number and location of individual dopants and defects to a resolution of one atom. Because of this difficulty, there is much interest in fabricating single-electron transistors (SETs) by molecular self-assembly. Here, the critical requirements involve the molecular orientation and chemisorption energy, molecular structure, and corresponding energy band structure. The concept of energy band analagous offsets and absolute reference levels in molecular structures will be an important topic of investigation in this emerging field.

Table 8.1 summarizes the drivers for and main issues in the development of nanoscale devices.

Table 8.1
Critical Issues in Development of Nanoscale Devices

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Published: January 1998; WTEC Hyper-Librarian