Site: Hitachi Central Research Laboratory
Tokyo 185-8601, Japan
Date Visited: 22 July 1997
WTEC: E. Hu (report author), L. Jelinski, C. Koch, D. Shaw, C. Uyehara
- Dr. Shigeo Nagashima, Deputy General Manager and Head of the Planing Office
- Dr. Tadashi Ikeda, Head, Research Cooperation Center, Planning Office
- Ms. Yuko Nakamura, Research Cooperation Center, Planning Office
- Dr. Masanobu Miyao, Head, Electronics Material Center, Electron Devices Research Department
- Dr. Toshio Katsuyama, Sr. Researcher, Optoelectronics Research Department
- Dr. Atsushi Kikukawa, Research Scientist, Advanced Research Laboratory
- Dr. Masaaki Futamoto, Chief Research Scientist, Information Storage Research Department.
- Dr. Kazuo Yano, Sr. Researcher, Systems LSI Research Department
The Research Cooperation Center Planning Office of Hitachi Central Research Laboratory hosted the WTEC team's visit. We were greeted by Dr. Shigeo Nagashima, Deputy General Manager and Head of the Planning Office. Exact figures were not available as to the representation of nanotechnology research at Hitachi.
RESEARCH AND DEVELOPMENT HIGHLIGHTS
Dr. M. Miyao discussed enhancement of light emission from SiGe quantum well devices:
- there is a correlation of poor light emission with long Ge-Ge correlation length: there is a local change in strain, hence a change in band structure
- atomic hydrogen is used as surfactant to change the correlation of Ge and Ge
- the goal is to achieve optoelectronic devices and/or high speed electronic devices with abrupt interfaces
Dr. T. Katsuyama gave a presentation on exciton-polariton quantum wave devices, with confinement within quantum wires. He discussed a novel means of forming the quantum wires, or quantum whiskers:
- evaporate thin layers of Au dots onto GaAs (or InAs) surfaces, form clusters, then alloy of Au-In-As or Au-Ga-As liquid droplets: this preferentially absorbs precursor gases (arsine, TMGa), to selectively grow whiskers
- the whiskers are 15 nm in diameter, 1.5 Ám in length - broad PL, no reduction in luminescence; the wires are so good because of slow surface recombination due to a high surface potential barrier
- the direction of growth is parallel to (111)B ¾
so they can grow perpendicular or parallel to the substrate surface
- In, Pt, and Ni do not work; he and his colleagues have made p-n junctions (23pF)
Dr. A. Kikukawa discussed some means of ultrahigh density recording using atomic force microscopy (AFM) indentation (Figure D.1).
Figure D.1. Concept for high density data recording using nano-indentation (Hitachi).
- force modulation AFM on polycarbonate: this yielded 40nN, 60 Ás pulsed width, a minimum diameter of 8 nm diameter, and 25 nm pitch
- readout with AFM: this required reducing cantilever sizes to operate with higher frequencies for rapid read out (1-2 MHz for 20 Ám length cantilevers). Note: few groups in other labs have been working on and successfully addressing these issues.
- he showed a readout at 1.25 Mb/s, 100 rpm, 25 nm pit size, and a chart of yield vs. technology ¾
with this indentation technology having 100% reliability
Dr. M. Futamoto gave an excellent presentation on "near-term" issues for improved materials for magnetic storage (with charts, etc.).
- he showed charts on trends of recording areal density, and decreasing trends of recording minimum size unit; the estimated requirement is 10 GB/in2 by when and 40 GB/in2 by 2010 (Figure D.2)
- CoCr16Ta4 : Dr. Futamoto showed TEM with 20-30 nm grain size, EDAX of grain boundaries and intergrain showing more Cr at the boundaries, and EELS maps of elemental distributions (Figure D.3)
- approach: make the recording thin film thicker, and use magnetization perpendicular, rather than parallel to the plane of the recording medium
Figure D.2. Need for storage capacity, in bytes (Hitachi).
Figure D.3. Perpendicular recording using CoCrTa (Hitachi).
- Cr segregation increases as substrate temperature increases
- 100 kiloflux change/inch (current) ¾
> 300 kFCI up to 500 kFCI
- spin-valve head
- spin valve structure: need thin layers with sharp interfaces, can obtain < 5% variation in thickness over 6" wafer (Figure D.4)
Dr. K. Yano discussed single-electron memory schemes (Figure D.5). He had previously worked at ASU with Ferry.
- He described work on novel polysilicon transistors: nanosilicon (Figure D.6)
- ladder-shaped memory cell array (Figure D.7), based on single-electron transistors ¾
selective read/write of certain bits 0.8 x 0.5 Ám2 cell: need selective read-write of certain bits
Figure D.4. Spin valve structure.
Figure D.5. Single electron memory concept.
Figure D.6. Polysilicon transistors.
Figure D.7. Ladder-shaped memory cell array.
The WTEC team's hosts were pessimistic about single-electron logic, stating that reliability requirements are severe. They stated that memory is different ¾
it is possible to use conventional CMOS circuitry to insert different cell structures.
Published: September 1999; WTEC Hyper-Librarian