Even though the study of single-electron charging effects with granular metallic systems dates back to the 1950s, it was the research of Likharev and coworkers almost 10 years ago that laid much of the groundwork for understanding single-charge transport in nanoscale tunnel junctions (Likharev 1988; Averin and Likharev 1991, Chap. 6). The concept was developed of a Coulomb gap that can be exploited to control the transfer of single charges. Since then, many research groups have made use of the Coulomb blockade effect to develop SED technology. Figures 5.2 through 5.11 show some of the myriad approaches to developing SEDs and representative laboratories pursuing the various SED concepts. Some of the more recent results are discussed below.

The group at Hitachi Europe uses a side-gated constriction in a delta-doped GaAs structure to fabricate a magnetic tunnel junction device in which a series of small islands separated by tunnel barriers are formed (Nakazato et al. 1992) (see, for example, Fig. 5.2). At ~ 2 K, the Coulomb gap voltage oscillates as a function of the side-gate voltage. Using the MTJ device as a building block, both memory and logic (inverter, NOR) functions have been demonstrated (Nakazato 1996, 65). The fabrication procedure makes use of standard semiconductor processing techniques and does not rely on lithography to define the nanoscale islands, since these are created by disorder in the delta-doped layer.

Other groups have utilized fine-line lithography to fabricate SEDs. At IBM, a flash memory SED was demonstrated by fabricating a sub-50 nm Si quantum dot (QD) on top of a MOSFET channel using a silicon-on-insulator (SOI) substrate, with the QD acting as a floating gate (Wesler et al. 1997). Single-electron charging was observed up to 90 K, while large threshold voltage shifts of up to 0.75 V were measured at 290 K. The University of Minnesota and Fujitsu have also reported similar structures (Guo et al. 1977; Nakajima et al. 1997). To overcome the lithography limitation on the QD size, the Toshiba group used a Si edge quantum wire approach (Ohata and Toriumi 1996). An inversion layer was formed at the 15 nm high Si sidewall of a SOI structure by growing a gate oxide and depositing a poly-Si gate there. Conductance oscillations were clearly seen at 4.2 K in this edge-channel MOSFET (Fig. 5.3). More recently, the Toshiba group has reverted back to a more planar device configuration, with a 50 nm wide Si quantum wire defined by e-beam lithography and oxidation of the surrounding SiO2 (Koga et al. 1997, 79).

One method to form semiconductor QDs without depending on fine-line lithography is to make use of the self-organizing nature inherent in the Stranski-Krastanow thin film growth mode. In the initial stages of the heteroepitaxial growth of lattice-mismatched materials, strain-induced coherent relaxation occurs and dislocation-free islands are formed that are in the tens of nanometers range in size. There has been considerable research in these self-organized quantum dots (SOQDs) in the past few years, though much of the work has been of a fundamental nature (see, for example, Petroff and Demmester 1995; Nötzel 1996). More recently, the University of Tokyo has proposed the embedding of InAs SOQDs in AlGaAs/GaAs heterojunction field effect transistors (HFETs) to form a flash-memory SED (Sakaki et al. 1995).

Figure 5.2
Metal colloids, self-assembled monolayer (SAM) coatings, polysilicon, quantum dots embedded in SiO2 (Hitachi, IBM, RIKEN, NTT, ETL, University of Lund).


Figure 5.3.
Sidewall extensions of MOSFET gate (Toshiba).


Figure 5.4.
Oxidation of metal or semiconductor with scanning tunneling microscope (STM) tip (ETL).


Figure 5.5.
STM probe oxidation of metal on vicinal substrate steps (ETL).

Figure 5.6
Double barrier tunnel diode structure (Max-Planck-Institut, Stuttgart; NTT).


Figure 5.7.
Gated double barrier tunnel diode structure (Max-Planck-Institut, Stuttgart; NTT; Purdue University).


Figure 5.8.
Depletion layer control of 2DEG area (Hitachi, University of Glasgow, University of Tokyo).

This concept was further demonstrated by the Sony group, which reported observing threshold voltage shifts at 300 K (Taira et al. 1997, 53). Fujitsu has also proposed the use of InGaAs QDs in a similar manner (Futatsugi et al. 1997, 46). The one difference in this case is that the QDs are formed at the bottom of tetrahedral-shaped recesses formed by substrate patterning. Since SOQDs form in a somewhat random manner on a planar surface, this approach provides positioning control.

Figure 5.9
Tetrahedral shaped recess, TSR (Fujitsu).


Figure 5.10
Double barrier metallic SET patterned by e-beam (NEC).

Of course, QDs can be formed with materials other than semiconductors. In fact, some of the earliest work in single-electron charging was done with metallic tunnel junctions. With modern fabrication tools and techniques, some groups have investigated the formation of nanoscale Au particles between metallic contacts. The University of Cambridge group used focused ion beam deposition to place Au dots between electrodes spaced 30 - 40 nm apart (Woodham and Ahmed 1997, 73). At Lund University in Sweden, atomic force microscopy (AFM) is utilized to move a 50 nm Au particle in between contacts formed by e-beam lithography (Carlsson et al. 1997, 128). Researchers observed conductance plateaus stable for several minutes at 300 K. The group at Cambridge University/Hitachi Europe used a colloidal process to form a chain of insulated Au particles between source, drain, and gate electrodes (Tsukagoshi et al. 1997, 67). At 4.2 K, the chain exhibited a Coulomb staircase and periodic conduction oscillations in I-V measurements.

For a very different approach, a molecular embodiment of a QD-based system can be realized by connecting a single molecule between metallic contacts. At Yale University a single molecule of benzene-1,4-dithiol was self-assembled from solution onto two electrodes of a mechanically controllable break junction (Fig. 5.11, left) (Reed et al. 1997). The spacing between the electrodes is ~ 0.8 nm, and I-V measurements at room temperature showed a gap ~ 0.7 V wide, which is attributed to a Coulomb gap. The Delft University of Technology in the Netherlands is also working on transport through oligomers (Fig. 5.11, right).

Figure 5.11
A single molecule connecting metallic contacts (Yale University, University of South Carolina, Delft University, Karlsruhe University).

Concerning the architecture in which SEDs are utilized, a number of approaches have been proposed. One of the more novel ideas is that of quantum cellular automata (QCA), based on some earlier work at Texas Instruments and developed at the University of Notre Dame (Lent et al. 1993; Tougaw and Lent 1994). The basic QCA cell is made up of a group of capacitively coupled QDs. Each cell holds two electrons, resulting in two polarization configurations that can represent the logic "0" and "1" states, and each cell interacts via Coulombic forces with neighboring cells. An array of cells can then be used to transmit binary information, which eliminates the need for physical interconnects between devices and represents a paradigm shift for ultralarge-scale integration (ULSI). Basic Boolean operations (AND, OR, etc.) can be implemented using QCA, and more complex functions have been simulated. Most recently, the Notre Dame group has demonstrated a nonlinear, bistable response of a QCA cell, albeit at a very low temperature of less than 20 mK (Snider et al. 1997, 233).

The QCA approach is not without its challenges (and critics). Circuit fabrication will be difficult because stringent control in QD positioning is required. Others have pointed out that bistability is only a necessary but not sufficient condition for the operation of Boolean logic circuits, because isolation is needed between the input and output, while background charge fluctuations will hamper logic implementation (Roychowdhury et al. 1966; Barker et al. 1997, 233). Thus, there is also considerable research in the use of SEDs with more conventional architectures. The group at Hitachi Europe uses its MTJ devices in binary decision diagram logic that is commonly used in large-scale integrated (LSI) circuits (Tsukagoshi et al. 1997, 67). The Toshiba group is combining its SED with a MOSFET to compensate for the lack of gain in the former, as are, presumably, other groups working on QD-based flash memory SEDs (Koga et al. 1997, 79). Tables 5.1 and 5.2 summarize some of these approaches.


Table 5.1
SET Architectures

Flash Memory

Digital Logic

Cellular Automata

Neural Networks


Hitachi (binary decision diagram logic)

Notre Dame


Delft U. Technology


Hokkaido University






Table 5.2
Quantum Dot Flash Memory













QD Material






QD Fab Method

E-beam / etch

E-beam / etch

E-beam / etch

E-beam / etch

Epitaxial self-assembly

QD Size (nm)

10 (estim.)

7 x 7 x 2 h

30 x 20 x 25 h

30 x 20 x 8 h

25 x 4 h

2Vth (V)

0.5 - 1.0





Write/ Erase

15 V / 10 V

> 4 V

4 V

3 V

> 1 V


1 - 24 h

10 sec.


> 1 wk

10 sec.


128 Mb LSI



In summary, while significant progress has been made in nanofabrication techniques, the field of single-charge electronics is still limited in scope by the lack of a suitable architecture that fully utilizes the unique aspects of single-electron charging. Current approaches require many SED elements to achieve conventional functions such as adders, exclusive NORs, etc. Simulations of such circuits predict slow operating speed. The field seems to be stuck on applying conventional electronics to SEDs. Either a new architecture will be discovered or SEDs may find a niche home in those applications where measurements of single charges are needed.

For the fabrication of nanoscale electronic devices, the self-organizing technique appears to be the most promising. The field of self-organized semiconductor QDs is quite active, but aside from optical emitters, very few practical electronic functions have been proposed. Of those, the single-electron flash memory is attracting attention, but there has been no serious proposal as to how the device could operate under normal integrated circuit performance conditions and reliability specifications. Using the SED as a floating gate to a MOSFET has the same kinds of problems as applying conventional approaches to SED architectures; until someone comes up with a better idea, the future of these approaches remains to be determined.

Published: September 1999; WTEC Hyper-Librarian