PREFACE

This report of the Japanese Technology Evaluation Center (JTEC) began in late 1992 when four agencies of the United States government contacted JTEC to request a study of high-volume, low-cost electronic packaging in Japan. The four agencies that contracted this study were the Department of Commerce (DOC), the National Science Foundation (NSF), the National Aeronautics and Space Administration (NASA), and the Advanced Research Projects Agency (ARPA) of the Department of Defense (DOD). During a meeting held in Washington, DC, on January 8, 1993, representatives from the sponsoring agencies (listed in Appendix D) met with JTEC staff to identify their respective interests in the study. DOC through its charter to assess and report on Japanese technology, and NSF as the lead agency for JTEC, both were primarily interested in the technologies of electronics packaging in Japan; NASA was primarily interested in the reliability of electronics components for spacecraft; and ARPA was primarily interested in assessing the relative strengths of commercial industrial electronics products in the United States and Japan, because of DOD's commitment to increase procurements of affordable components in the commercial marketplace. The representatives from the four sponsoring agencies agreed that the basic goal for the study should be identification of the factors that have made Japan so successful in the field of high-volume electronics.

On request from the sponsors JTEC sought industrial input on the value of such a study to U.S. industry. Dr. Michael J. Kelly, Director of the Manufacturing Research Center at Georgia Tech, agreed to chair the JTEC Electronics Packaging Panel and to organize the meeting to solicit recommendations from the industrial sector. The meeting was held in Washington, D.C., on April 19, 1993. Attendees (listed in Appendix E) generally agreed that Japanese competitive advantages in electronics are based on more than technology. They argued for a study that also investigated the impact of infrastructure, management, investment, and government policies on Japan's dominance in the electronic marketplace. In response to these recommendations, JTEC selected a panel of experts with diverse backgrounds that would enable them to address multiple facets of electronics manufacturing and packaging in Japan. Following is a brief biography of each of the panel members. More detailed biographies of the panelists and of other participants in the Japanese site visits are included in this volume as Appendices A and B, respectively.

Dr. Michael Kelly, the panel chair, is Director of the Manufacturing Research Center at Georgia Tech. Prior to his present position he was Director of the Defense Manufacturing Office at the Advanced Research Projects Agency at the Department of Defense. He worked for IBM between 1969 and 1987.

Dr. William Boulton is a professor of strategic management and Director of the Center for International Commerce at Auburn University. Dr. Boulton has spent seven years in managerial and academic positions in Japan, including Visiting Scholar at Japan's Ministry of Finance's Institute for Fiscal and Financial Policy, and Visiting Professor at Keio University's Graduate School of Business Administration.

Mr. John Kukowski is a corporate fellow at Universal Instruments Corporation, where he also held the position of Vice President of Advanced Technology. Mr. Kukowski is presently on sabbatical at Rochester Institute of Technology, where he is assisting in the development of an interdisciplinary electronics design and manufacturing program.

Dr. Gene Meieran is an Intel Fellow whose knowledge of the electronic "food chain," beginning with materials, has established him as a leader in the electronics industry. In addition to his Intel responsibilities, Dr. Meieran is also Director of Research for the MIT Leaders for Manufacturing program.

Dr. Michael Pecht is a professor at the University of Maryland where he is also founder and director of the Computer Aided Life Cycle Engineering (CALCE) Electronic Packaging Research Center. Dr. Pecht is chief editor of IEEE's Transactions on Reliability.

Dr. John Peeples is an Assistant Vice President of Manufacturing for AT&T Global Information Solutions (formerly NCR) and Director of the Manufacturing Technology Research Center. Dr. Peeples is also the leader of the Director of Engineering Peer Team for the General Purpose Product Group.

Dr. Rao Tummala is a recognized expert in high-performance electronic packaging who, as an IBM Fellow, was responsible for IBM's advanced electronic packaging program. Dr. Tummala is now a chaired professor in the Electrical Engineering Department at Georgia Tech.

On May 4, 1993, the JTEC electronics packaging (EP) panel met with its sponsors and JTEC staff in Washington, D.C., to clarify the objectives of the electronics packaging study. The attendees identified four primary areas for assessment:

1. Japanese technology priorities and roadmaps

2. Japanese product realization processes, with specific attention to notebooks, personal digital assistants, camcorders, and cellular telephones

3. Japan's competitive advantages related to manufacturing and production technology

4. Japan's competitive advantages related to infrastructure and management support systems

Dr. Gene Lim of SEAM International worked closely with the panel to arrange meetings with appropriate companies in Japan between October 1-9, 1993. The panel members were joined in Japan by Dr. Nick Naclerio of ARPA; Mr. Phil Barela of NASA; Mr. George Harman of DOC; Dr. Linton Salmon of NSF; Dr. Duane Shelton of JTEC; and Dr. Lim. Subsequent to the site visits, panelists and other team members generated a report on each site. These site reports are included in this report as Appendix C. JTEC held an open meeting in Washington, D.C., on January 12, 1994, during which the JTEC Electronic Packaging Panel reported its preliminary findings.

Following the workshop, the panel members prepared the first draft of the written report that is published in this volume. Both the site reports and the draft chapters were subjected to an extensive review process. During the course of this review, extensive new and updated information was added by both Japanese hosts and panel members. During proofing of the report prior to publication, more new information derived from recent publications was added. The end result that follows is the JTEC panel's final evaluation.

The content of the analytical chapters of this report, Electronic Manufacturing and Packaging in Japan, was contributed by the panel members. Michael Kelly prepared the Executive Summary; William Boulton edited the chapters in draft. The authors of the body of the report are as follows: William Boulton describes the importance of the electronics industry to global competition in Chapter 1, High-Volume Low-Cost Electronic Packaging. Dr. Boulton also provides a conceptual understanding of the product development problems for electronics as described in Chapter 2, Building the Electronic Industry's Roadmaps. Gene Meieran, William Boulton, and Rao Tummala developed Chapter 3, Japan's Technology and Manufacturing Infrastructure, to describe some of the underlying strengths of Japan's electronic industry. Rao Tummala and Michael Pecht provide the technological descriptions in Chapter 4, Japan's Electronic Packaging Technologies. John Kukowski and William Boulton offer a description of Japan's electronic manufacturing capabilities in Chapter 5, Electronic Manufacturing and Assembling in Japan. Michael Pecht and William Boulton are the authors of Chapter 6, Quality Assurance and Reliability in the Electronic Industry. John Peeples and William Boulton contributed the material for Chapter 7, Successful Product Realization Strategies.

The authors of this report are deeply indebted to the large number of people who contributed to its preparation. We extend our sincere thanks to our Japanese hosts who so graciously gave of their time in sharing information about their respective companies. We also appreciate the cooperation of the sponsoring agencies and the contributions of their representatives who accompanied the JTEC panel; these were major factors in the successful development of the report. We are greatly indebted to Dr. Gene Lim who made the excellent trip preparations to Japan and accompanied us during our visits to the Japanese companies. Finally, the panel members wish to express our appreciation to all the members of the JTEC staff, especially Geoff Holdridge, for their cheerfully given support in preparing for the study, executing it, and publishing the results.


Published: February 1995; WTEC Hyper-Librarian