Date Visited: October 6, 1993
Report Author: J. Peeples
Our visit was divided into three distinct sessions: a tour of the Circuit Manufacturing Technology Lab of the Corporate Production Engineering Division, a tour of a chip size inductor factory, and a discussion on chip mounting technology. The JTEC visit began right where my visit in 1990 had ended, in the Circuit Manufacturing Technology Lab, one of five subdivisions of the Corporate Production Engineering Division.
Mr. Murakami discussed the process development plans. Some of his handouts were identical to those I had been shown in 1990, only updated to show progress. Panasonic, like most of the Japanese companies I visited, seemed to have a remarkable degree of strategic technological consistency. My opinion is that similar U.S. companies are less likely to invest long-term in specific technologies, but would rather jump to new "promising" alternatives.
Mr. Hiroshi Asai, Manager of the Marketing Department, gave us a rough sketch of Matsushita:
We were each presented a copy of My Management Philosophy by Matsushita's founder, Konosuke Matsushita. It is 66 pages full of gems of wisdom. Following are some of the quotables:
The Circuit Manufacturing Lab is the process and equipment development arm of Panasonic Factory Automation. It develops whatever is necessary to service new products. Much of the work in process is for palmcorder or for flat panel applications. We were told that about 20 engineers may be involved for three months to transfer a new FA line into production.
The lab we visited is set up for touring. A graphic arts display emphasized the importance of the Panasonic solder paste development to its fine-pitch (0.3 mm in production) stencil, place, and reflow process. The key point was that Panasonic has achieved a more spherical solder particle shape than normal, allowing the paste to have more predictable flow characteristics. Our hosts were excited about this and were similarly excited about their in-house-developed conductive epoxy; neither of these formulations are available for sale in the United States.
This lab exhibited the latest equipment technology for FA. New since my 1990 visit is the emphasis on lower-cost methods of direct chip attach and an increased involvement with glass substrates. Panasonic is using normal wirebonders with a special shear cycle to attach a gold ball bond to an IC pad and immediately shear the wire at the top of the ball. This leaves a small tail (like a Hershey's Chocolate Kiss), which is then flip-mounted into conductive adhesive sites on a glass substrate. The process requires no tooling or wafer-level processing.
Another area that has developed dramatically since my last visit is the film area. Panasonic has put TAB into full use as a glass and PC board interconnection media. It has special equipment for what our hosts refer to as FOG (film on glass) and FOB (film on board). Both technologies are demonstrated as applied to flat panel display production. LCD drivers are mounted to a sliver of PC board material. A TAB interconnection is first hot bar bonded to the glass flat panel using anisotropically conductive adhesive tape. The other end of the TAB is then pulse laser bonded to the driver PC boards. With FOG and FOB, Panasonic has in place the first fully automated LCD assembly line in the world. The current line does a single edge of the LCD per cycle. The new generation will assemble all three edges simultaneously.
The Circuit Manufacturing Technology Lab, as a corporate staff function, provides assistance to all system divisions across the Matsushita group on SMT fine-pitch process and equipment development. It is primarily intended to enhance Matsushita Electric's manufacturing capability in order to increase its competitiveness. Membership is 600,000 yen annually, open only to Matsushita's system divisions, its subsidiary companies, and its affiliated companies, not to any party outside of Matsushita, regardless of whether it is a domestic or overseas entity.
Almost as an aside, we were given a tour of a factory of SMT mountable inductor coils. This facility was extremely noisy. Wireless headsets must be worn in order to hear the tour guide. Fine wire is automatically wound on a core that is terminated to a continuous leadframe and encapsulated. These are moved around on reels of 40,000 parts each. Parts are marked and visually inspected by computer, then excised from the lead frame and tested and binned. Velocity and quality are very high. Relatively large numbers of people are involved in this production.
Process improvements seem targeted at further integration of processes. The current process demands loading the test station from a parts feeder after excising from the continuous leadframe. After testing, parts are once again binned into parts feeders for final packaging. The new process will trim and test the parts and put them directly into rails to be packaged without the parts feeders. This new method reduces the space required for trimming, testing, and packaging by 10 square feet; floor space reduction was mentioned as a key reason for the improvement. As this station is replicated many times, this results in a significant utilization opportunity. One-fourth or more of the floor space appeared to be dedicated to test stations.
Mr. Hiroaki Fujimoto, Senior Engineer of the VLSI Technology Research Lab, discussed transfer bump, micro bump, stud bump, and new bonding methods for chip assembly to substrates. Transfer bump is a method developed by Matsushita to displace the need for wafer scale processing to form the gold bumps required for TAB inner lead bonds. Gold bumps are formed on a glass substrate and transferred to the inner lead of the TAB frame via thermo-compression prior to inner lead assembly. Matsushita has marketed transfer bump worldwide for several years now.
Micro bump technology is a flip chip method that uses adhesive shrinkage to electrically and mechanically connect the interconnection bumps to a typically glass substrate. Micro bump uses glass and ceramic substrates. The adhesive is photo-curable; thus a more transparent substrate is naturally preferred, but edge-wise illumination will work with opaque substrates. Micro bump is currently in use in thermal print head assembly and is capable of 10 micron lead pitch.
Mr. Yoshihiro Bessho, Engineer for the Materials and Components Research Laboratory spoke on the stud bump bond (SBB) method of attachment. SBB employs the sheared gold ball bonds mentioned earlier to adhesively mount the chip to a variety of substrates. This technology is limited to pitches greater than 100 microns but is extremely flexible and simple in application. The ball bond studs are dipped into conductive adhesive and then glued to substrate. The wire bond "tails" are allowed to set the conductive paste penetration depth and apparently can do so accurately enough that bridging between bonds is not a problem. An undercoat adhesive more firmly secures the overall system.
Similar to what we saw and heard at Sony, Matsushita views process development on a par with product development. The Corporate Production Engineering Division (Circuit Manufacturing Technology Lab), reports at the highest level of the company and appears to be marketing what is considered a corporate core competency. As mentioned earlier, the consistent pursuit of a technological strategy is striking. The laboratory's dedication to fine pitch or to transfer bump or other low-cost flip chip technologies is long-term and not likely to be redirected or curtailed short of the set objectives. The Matsushita strategy seems to be a familiar one: make it small and cheap!