E.1 Mass production strategy for low-cost electronic products

1.1 1991 global electronics production; the four largest electronics regions
1.2 Japan's trading relationships in 1993
1.3 The movement of Japanese production facilities offshore
1.4 Japanese forecast of audiovisual production in 1995 and 2000
1.5 Number of computer-related systems worldwide
1.6 Microelectronics world market structure 1990

2.1 Strategic objectives for product development
2.2 First-to-market advantages
2.3 Financial advantages for product leadership
2.4 Next-generation product roadmaps
2.5 Market-driven demands for electronic packaging

3.1 Japan's successful production development strategy
3.2 Parallel product development strategies in Japan
3.3 TDK's product development strategy
3.4 Japanese passive component strategy
3.5 Japan's product development strategy
3.6 Moore's Law of Active Element Density
3.7 PC board component density
3.8 Hitachi's distribution of R&D funds
3.9 Hitachi's Strategic Business Projects System

4.1 Japan's technological and market leadership
4.2 Japanese competitive advantage from breadth of technology
4.3 Mass production strategy for low-cost electronic products
4.4 Electronic packaging trends
4.5 Single chip packaging costs
4.6 Current development trends of epoxy molded compounds
4.7 Ceramic packaging trends
4.8 Consumer ceramic substrate
4.9 Low-cost ceramic co-firing process with copper
4.10 Consumer ceramic substrate with Cu
4.11 Multilayer ceramic (MLC) and printed wiring board (PWB) compared
4.12 Hollow structure in ceramic for improved dielectric constant
4.13 Propagation delay versus dielectric constant
4.14 Package design improvement
4.15 Ceracom substrate with low TCE and low dielectric constant
4.16 Components trend in camcorders
4.17 Overall Japanese packaging strategy
4.18 Flip chip processing conductive adhesive
4.19 QFP-MCM in ceramic
4.20 Wiring density comparison between PWB/ceramic
4.21 Low-cost fine line thin film process
4.22 Shape and accuracy of conductor pattern by additive process
4.23 Additive process enhancement
4.24 Anisotropic conductive conductor system
4.25 Nitto process for TAB
4.26 Nitto bump making process
4.27 Microprocessor carrier (BGA) for LSI
4.28 Bump fabrication process
4.29 Effects of encapsulation on strain in solder
4.30 Effects of encapsulation and solder composition on strain in solder
4.31 Japanese consumer product component density trend
4.32 Soldering defect improvement achieved at Oki
4.33 Soldering technology trend in Japan
4.34 Package weight versus pin count
4.35 Lead pitch and mounting height
4.36 High pin count packages
4.37 Relative package areas: BGA versus QFP
4.38 Japanese high pin count strategy
4.39 Japanese packaging assembly strategy

5.1 Japan's development of computer-integrated manufacturing
5.2 Japan's surface mount devices
5.3 Japan's SM applications of major components
5.4 Major companies comprising Japan's surface mount infrastructure
5.5 Japan's surface mount developments
5.6 Next-generation surface mount technology
5.7 Predominant pitch capability for low-cost electronic packaging

6.1 Cause-and-effect diagram

7.1 Japan's product development activities
7.2 Concurrent development requirements
7.3 Functional integration required for technological innovations
7.4 Concurrent engineering for product innovation
7.5 Murata's integrated technology strategy
7.6 Sony's concurrent development model
7.7 Sharp's expanding LCD applications
7.8 NEC's technology planning process
7.9 NEC's contract and budget process

Published: February 1995; WTEC Hyper-Librarian