CHIP ASSEMBLY TECHNOLOGIES

Japan is practicing chip assembly in more ways than does the United States. It is pushing wire bonding to its limits and is highly successful in the use of TAB, having applied it from consumer to supercomputer packaging. The Japanese have applied and continue to apply flip chip both with solder and with conductive adhesive technologies. In addition, they are continuing to push chip on board, not only by wire bonding the chip to the board, but also by TAB bonding to board and flip chip solder bonding to organic board. In a new development Fujitsu is offering its BIT system for notebook computer applications.

Table 4.12 demonstrates Oki Electric's development plan, typical of most large Japanese companies, for all three technologies - wire bond, tape automated bonding, and flip chip. It sets the development goals for wire bond by ball bond and wedge bond technologies at a pitch of 50 microns and for TAB at a pitch of 75 microns. Japan expects to push wire bond up to 1200 I/Os on a 20 x 20 mm chip using a staggered pin configuration.

Table 4.12
Japanese Chip Assembly Plan (Oki)

The progress and trend in TAB listed in Table 4.13 show two or more layers with an inner lead bonding pitch of 60 microns and an outer lead bonding pitch of 90 microns. On a 28 mm size chip, these leads provide in excess of 1100 I/Os. Various advancements in TAB technology are being pursued by such Japanese companies as Shinko-Denshi, NEC, Fujimitso, Mitsui-Kinzoku, Oki, and Nitto Denko.

Table 4.13
Japanese TAB Package (TCP) Characteristics (Oki)

One particular enhancement of TAB being pursued by Nitto Denko is illustrated in Figure 4.25, comparing the new two-layer direct copper bonding process with a conventional three-layer process. The new process coats polyimide onto copper, the opposite of the 3M process in the United States that coats copper on Kapton or other polyimides by electroplating. The advantages of this new process, shown in Table 4.14, include high heat resistance, low moisture absorption by proper selection of polyimide, and better adhesion. There are other advantages to using this new process: (1) a very high aspect ratio - 25 micron diameter holes in a 50 micron thick film; (2) large area processing (300 x 300 mm); and (3) complete wiring patterns (both vias and lines). Nitto is also applying this technology for burn-in electrical testing, as illustrated in Figure 4.26.


Figure 4.25. Nitto process for TAB.

Table 4.14
Advantages of the Nitto Process


Figure 4.26. Nitto bump making process.

Flip chip technology is being extensively studied by almost all major Japanese firms and is already used in products by Hitachi and IBM (Japan). The Hitachi flip chip, together with microcarrier BGA assembly to next-level package (mullite glass-ceramic), is illustrated in Figure 4.27. The microcarrier, which is only bigger than the chip itself by about 2 mm, is a single-chip carrier fabricated with seven-layer mullite ceramic and five levels of polyimide-aluminum thin-film technology. Flip chip enhancements being pursued by Japanese electronic companies generally consist of one of two approaches - solder bonding (including Pb-Sn, Pb-In), and conductor adhesive bonding. Bump technology itself, like Fujitsu's bump integration technology (BIT), is generating considerable interest. One example is illustrated in Figure 4.28 using thin-film and electroplating processes. In contrast, the Germans are pursuing electroless-plate bumping, while the British are trying gold ball bumping by wire-bonding tools.


Figure 4.27. Microprocessor carrier (BGA) for LSI (Hitachi).


Figure 4.28. Bump fabrication process (Sharp).

The flip chip bonding receiving the greatest interest in Japan is the technology IBM (Japan) pioneered as an extension of IBM (U.S.) flip chip technology developed three decades ago. It involves direct bonding of a bumped chip to a PWB by the use of low- temperature solder that is hot-injection-deposited onto PWB through a mask. The challenge here is to develop a thermally compatible encapsulant to reduce the strain on the solder joint arising from the great mismatch in thermal expansions between PWB (17 PPM) and chip (3 PPM).

Figure 4.29 illustrates a tenfold strain reduction when the encapsulant is used between the PWB and the chip. This discovery has major implications for the Japanese packaging industry, particularly for consumer electronics, as it allows Japanese investments in PWB to be incrementally improved over the next decade. Figure 4.30 shows the eutectic solder to be more effective than high-Pb solder (95/5) in achieving the desired fatigue life.


Figure 4.29. Effects of encapsulation on strain in
solder (IBM Japan).


Figure 4.30. Effects of encapsulation and solder
composition on strain in solder (IBM Japan).

Japanese manufacturers have used and continue to use chip-on-board technology using wire bond to PWB.


Published: February 1995; WTEC Hyper-Librarian