Multichip packaging is being developed to meet the demands for higher performance and further miniaturization. These design developments apply array technologies, SMT, and a variety of plastic, ceramic and thin-film materials. Advanced technologies like BGAs and MCMs have historically been limited to applications in high-performance products like supercomputers. Today, the Japanese are moving these technologies into lower-cost products through the use of MCM and chip-on-board (COB) applications using BGA connections for assembly and SMT mass production equipment. As shown in Figure 4.17, Japanese industry is pursuing multichip packaging technologies, but with applications using printed wiring and ceramic technology. Such integration of low-cost production is consistent with Japan's approach for low-cost product design and production, which encompasses three major issues.

Figure 4.17. Overall Japanese packaging strategy.

The first issue of integrated low-cost production design is that the silicon efficiency of MCM designs must be improved in terms of circuits or chips packaged per unit area. This goal can be accomplished by packaging ICs onto very-thin, compact, and lightweight microcarriers using area array connections, as shown in Figure 4.18.

Figure 4.18. Flip chip processing conductive adhesive (Fujitsu).

BGA provides advanced connector technology for use with SMT technologies. Large vertically integrated companies in Japan such as Hitachi and NEC have experience in multichip packaging using this microcarrier approach. Hitachi has used BGA for the central processing unit of its latest supercomputer and is confident in its quality. It has achieved silicon packaging efficiency in excess of 40%, which is about five times more efficient than the normal SMT approach. This technology is now being developed for applications in cost-sensitive consumer electronics products.

The second issue of integrated low-cost production design is that to exploit current wirebond, PWB, and SMT investments, many Japanese firms wire-bond chips onto a small MCM-type leadframe, as shown in Figure 4.19. This design is similar to ceramic and plastic packages using substrate materials, PWBs, and leadframes attached to QFP forms; the only difference is that each QFP contains two or more chips, typically 2-8 chips. This approach is referred to as QFP-MCM. In the United States, Motorola is offering 28 mm QFP-MCMs with 128, 160, or 208 leads and 40 mm packages with 232 or 304 leads. The lead pitch is typically 0.5 mm. Japanese companies exploiting this technology include Kyocera, NTK, and Sumitomo in ceramics, and Ibiden, Hitachi, and Oki in plastics.

Figure 4.19. QFP-MCM in ceramic (Oki, Kyocera).

The major advantage of QFP-MCM is its lower cost and ease of assembly with existing SMT manufacturing equipment. The MCM system, however, is expected to cost between 50% and 100% more than the single-chip QFP solution. However, QFP-MCMs are expected to meet demands for smaller size, better performance, and reduction in the number of system-level parts. Another advantage of QFP-MCM is that it needs no bumping technology. QFP-MCMs are typically made in 4 to 10 layers, each containing copper lines that are 75 microns wide, spaced 75 microns apart. The smallest drilled hole is 12 mils (300 microns). Power dissipation depends on the leadframe material and package design, but it is generally limited to 5 watts using PWB technology or ten times higher using ceramic technology. Part of the increased production of MCM components comes from Japanese firms' application of tape automated bonding (TAB) technologies for more accurate chip placement in the production of MCMs, rather than application of typical lower-cost wire bonding technologies.

The third issue of integrated low-cost production design is that three MCM developments in Japan are similar to ones in the United States: MCM-L (laminated PWB), MCM-C (ceramic), and MCM-D (thin-film dielectrics). These three generic technologies have already been applied in Japanese products from consumer electronics to supercomputers. The thin-film MCM-D has been applied by NEC with up to seven layers on a large 225 mm ceramic substrate, and by Hitachi on a microcarrier/interposer. Since these technologies are very expensive to use, efforts are currently underway by NEC, Hitachi, Fujitsu, Oki, NTK, Kyocera, Toshiba, and others to reduce the application cost.

Approaches to cost reduction include (1) development of lower-cost materials such as low-cost photosensitive materials, (2) development of large-area processing, as practiced in the fabrication of displays, (3) application of large-area lithography, and (4) application of low-cost metalization processes as practiced in PWB fabrication. Toray, Asahi Chemical, Sumitomo Bakelite, Hitachi Chemical, and Nitto Denko are aggressively pursuing polymeric developments, aimed at polyimides with low thermal expansion, very good mechanical properties, low water absorption, and good adhesion to ceramics and metals. The Asahi polymer, based on a modified BPDA-PDA chemistry, seems to meet all the required properties, including photosensitivity to g- and i-lines with 10 micron vias in 10 micron cured film. The resulting thermal expansion mismatch stress on a silicon wafer is about 30 MPa, about half that of conventional polymers. The cost per kilogram is around $600. Nitto Denko seems to have made further cost improvements through its novel-blended approach involving polyimide plus acrylic monomers and photo-initiators. The properties and relative costs of such dielectrics are listed in Table 4.10.

Table 4.10
Nitto Denko's Blend Polymer Dielectric

MCM-C is generally considered in Japan to be more cost-effective than thin film and provides a system-level solution for workstations based on superior wiring density, as illustrated in Figure 4.20. Toshiba, Hitachi, Fujitsu, NEC, and Oki are planning to apply this technology because of advantages like lower cost, lower electrical resistance, higher thermal dissipation, and higher reliability over MCM-L and MCM-D designs.

Figure 4.20. Wiring density comparison between
PWB/ceramic (Kyocera).

The primary advantage of ceramic over PWB (previously shown in Figure 4.11) is in the number of lines/vias per 100 mil channel, ceramic providing as many as 9 lines, each 100 microns wide, compared with 5 lines in PWB. But the Japanese are driving both technologies to much higher densities and to much lower costs. The technology improvements in PWB, however, come as process improvements as opposed to the development of parallel co-fire ceramic processes. Low-cost applications in VCRs and camcorders are beginning to appear using ceramic technology. Panasonic, for example, is already using its low-temperature ceramic components (LTCC) in peripheral tape memory systems and is expected to further apply it in cellular, automotive, camcorder, and computer applications. By using the LTCC as a lead-array hybrid (1.0 mm pitch) with through-hole mounting onto a PWB, Panasonic found it to be less expensive than the typical PWB approach. The embedded capacitors made of Pb(Mg(sub)1/3Nb(sub)2/3)O(sub)3-PbTiO(sub)3-PbO provide a capacitance of 30 nf/sq. cm. Canon camcorders have also used LTCC, presumably manufactured by Kyocera.

MCMs based on PWB technology are expected to be the most dominant because of prior investments and the existing infrastructure in Japan. The PWB base is being enhanced by (1) new materials, such as aramid fiber, BT resin, maleimide styryl, and photosensitive epoxy, (2) new processes such as additive plate and laser/photo vias, and (3) large-area, low-cost processing in not-so-clean facilities. These enhancements are in addition to those being pursued in conventional subtractive processes. The chip assembly to form multichip modules has already been practiced by direct wire bonding, TAB, and flip chip bonding of bare die. The wire bonding experience comes from consumer product COB, and TAB is employed in performance computers and consumer products. Flip chip is a recent introduction by Hitachi in its mainframes, and by IBM (Japan) in its PC products, wherein bumped chip is solder-bonded to PWB using eutectic solder. In addition, Fujitsu is exploring the same with conductive epoxy, eliminating both Pb solder and flux. In 1994, Mitsubishi's new cellular telephone used advanced flip chip assembly techniques.

Published: February 1995; WTEC Hyper-Librarian