With the development of enhanced materials and production methods, plastic packaging has become the low-cost, acceptable-reliability package of choice. Japan's electronics industry is committed to incremental continuous improvements in all areas of chip making and package assembly technologies. Professor Kenji Otsuka of Meisei University told the JTEC panel, "If we would lose packaging (plastic) technologies, we would get winter season for a long time."
Thin, small-outline packages, with their compact profiles, have become a key product of the 1990s. By most estimates, they will also be used increasingly in surface mount packages in the future, especially for memories, as demand for space-saving packages grows. Other thin package types include the thin quad flat pack (TQFP), thin sealed small outline (TSSOP), and thin-body plastic dual in-line (PDIP) packages. Integrated circuit packages with width and/or length shrink include the fine-pitch quad flat pack (FPQFP), quartersize small outline package (QSSOP), shrink dual in-line processing (SDIP), shrink quad flat pack (SQFP), shrink small outline package (SSOP) and very small outline package (VSOP). With these or new shrunken packages, suppliers will continue to provide more functions in less board space, and boards will become smaller. This trend to skinnier housings will challenge die thinning, wafer transportation, chip pad mounting, leadframe design, lead bonding, board interconnection, molding, and soldering technologies.
Continued development of plastic packaging technologies, as discussed above, is essential to support Japan's focus on low-cost consumer electronics products. As shown in Figure 4.5, plastic QFP remains the low-cost single chip electronic packaging technology. TAB is higher-cost but is utilized in cases where finer pitch is required to achieve miniaturization objectives. Ceramic pin grid array (PGA) is the highest-cost technology and is generally limited to uses where reliability and performance are critical.
Figure 4.5. Single chip packaging costs (Otsuka).
Present packaging issues depend on different uses for plastic quad flat packs (P-QFP) in Japanese and U.S. manufacturing. The U.S. Joint Electron Devices Engineering Council (JEDEC) is addressing the problems of bond pad pitch requirements finer than 0.65 mm (26 mils). A few Japanese manufacturers have tooled for 0.5 mm (20 mils) pitch parts and have plans for smaller pitch in various stages of development. The Electronic Industry Association of Japan P-QFP version has received wider acceptance by ASIC (application-specific integrated circuit) users and manufacturers, since greater volumes have been generated at lower costs than for the U.S. JEDEC version.
Plastic Molding Materials and Processes
As shown in Table 4.1, Nitto Denko is working to improve and develop molding materials to meet the needs of future packages. Manufacturing technology and the cost of advanced materials required for high-quality and reliable plastic packaging determine both acquisition and lifetime cost, and drive technology for the widespread use of plastic epoxy molded (PEM) packages in all markets. Performance criteria naturally adapt to the cost constraints of the market. The high-performance molding processes of the most common packages produces about 800 packaged devices per hour.
Molding Compound Development in Japan
Future packages using thinner leadframes, fine-pitch wire bonding, and flip chip or TAB structures will need low-viscosity molding compounds at low molding temperatures to reduce shear-rate-induced yield losses. Higher production rates are required to compete with PGAs and premolded packages. Smaller molds with fewer cavities and a total cycle time (including in-mold cure) of one to two minutes will be needed. A high level of automation will result in lower-cost, uniform-quality packages with less damage to fragile high-I/O-count assemblies. Clean manufacturing environments will also reduce contamination-related failures.
Automation will play an increasingly important role in PEM manufacturing in Japan. One approach is partial automation of various labor-intensive aspects of the process, such as preform heating and handling. A robotic arm may place the heated preform into the transfer pot and start the process sequence of transferring, curing, and ejecting the molded leadframes. In this automation approach, a single operator can handle four or five transfer presses. In the total automation approach, the process runs without any operator assistance, although typically 10 to 20% of an operator's time is spent moving different cassettes and checking equipment malfunctions. The use of a smaller molding tool with fewer cavities in conjunction with faster-curing molding compounds will further increase productivity. Such a packaging system is usually totally enclosed to maximize process cleanliness and personnel safety. The cassettes of molded leadframes feed an automated trim-and-form press and then move on to a code-marking station.
The partial or total automation of single-pot systems has been superseded by multiplunger technology in multiproduct production environments. In automated multiplunger systems, 6 to 12 pots feed 6 to 24 cavities, with 1 to 4 cavities per transfer pot. Because of the very short flow length, they are very effective in minimizing voids and promoting high molding compound density. State-of-the-art encapsulants, i.e., very fast-curing molding compounds with a total cycle time of less than two minutes in the molds, will be used in these manufacturing systems. Figure 4.6 shows the trend in encapsulant molding compounds.
Figure 4.6. Current development trends of epoxy molded compounds.
Process Controls and Quality Assurance
Stringent contamination control of package assembly components during fabrication of PEMs is necessary for quality assurance and long-term reliability. Over and above the practice of using semiconductor fabrication type class 100,000 or better clean-room operation, high-technology integrated-circuit wafer cleaning processes will increasingly spread into packaging process technology. Plasma cleaning of the pad and leadframe assembly for improved bonding with plastics may become widespread. As a function of oxygen/carbon tetrafluoride/argon plasma treatment, lap-shear strength of epoxy adhesives should increase. Ultrahigh purity chemicals are sure to find their way into PEM fabrication lines as initial cleaning agents for particulate contamination control.
The increasing use of analytical techniques and microsensors to fine-tune materials and control process-induced defects falls into the category of enhanced process control and quality assurance. X-ray radiography and C-mode scanning acoustic microscopy-tomography are finding increased use as nondestructive techniques for evaluating a number of processes: plastic delamination; die metal, die attach and bonding wire deformation; die metal and wirebond voiding; leadframe, die passivation, die attach, wire, wirebond and case brittle fracture; and dendritic growth under bias. Mercury porosimetry has also been used successfully to find the number and size of epoxy and epoxy-metal pores in epoxy-encapsulated packages. Epoxy pores are less than 0.2 micron in diameter, epoxy-leadframes voids are about 1 micron in diameter, and surface pores range from 5-500 micron in diameter. Piezoresistive strain gauges integrated into test chips will continue to be used to directly measure the mechanical stress induced inside a PEM by encapsulation, die bonding, and other factors, either during fabrication or under environmental stress testing. Solid-state moisture microsensors will also be used to measure the moisture content at any specific location inside a PEM.
Challenged by higher integration levels (particularly in ASICs) with tighter bond pad pitches at the die level, leading edge pitches will be at 0.060 to 0.075 mm (2.5 to 3 mils) by the late 1990s. Beyond 0.1 mm (4 mils) pitch, bonding with gold wire may be done by wedge bonding. The combination of tight pad pitches and shrink packages demands not only low wire looping (0.09 to 0.18 mm), but also different loop shapes. This requires modifying the dopants in the wire to offer the right set of mechanical properties. With tight pitches, the physical limits of leadframe technology will also force the placement of lead contacts at ever-increasing distances from the package center to control wire sweep. Low looping also promotes wire-to-die edge shortening when the die has inbound bonding pads to avoid encapsulation stress concentration zones. Edge shortening can be prevented by use of wirebonder software that allows an extra bend in the wire at the predetermined site.
The demands of tightly spaced inner-lead bonding (0.05 to 0.075 mm) and outer-lead bonding (0.15 to 0.35 mm), high pin counts, high-end performance-driven applications, and high-volume production, could also move bumped tape automated bonding (TAB) to the forefront of the packaging industry - a potential for which Japan already has the capability and infrastructure. Limiting factors for TAB application have been the expense of tape, the lead time needed to obtain it, and the capital needed for the bonding equipment. Bump fabrication has also been an obstacle. Better tape metallurgy, currently available, now permits burn-in and longer shelf life before encapsulation. Laser bonding of fine-pitch devices are particularly suited to TAB.
Trends in leadframe technology have important implications for the future of molded plastic packaging. Japanese companies are replacing copper alloys with 42Fe/58Ni (Alloy 42) as the leadframe material, especially for moderate to high heat dissipating devices such as processors and logics. For thin (less than or equal to 0.15 mm) leadframes with close lead tips for very high lead-count packages, chemical etching has replaced mechanical punching.
Plastic Packaging Advancements
New materials and component designs are required for continuous miniaturization. Tables 4.2 and 4.3 (following pages) show Nitto Denko's development roadmap for semiconductor encapsulating materials. As shown in Table 4.4, Ibiden's plan for future plastic PGA technology is expected to increase pin count from the current 500-600 pins to 2000 pins by the year 2000. This increase in pin count is possible with multilayer plastic packaging technology that includes new materials with lower dielectric constant and higher glass transition temperature, finer-line wiring, down to 25 micron lines on 100 micron pitch, and layer counts up to fifteen. Ibiden expects land grid arrays (LGAs) and ball grid arrays (BGAs) to approach 600 pins before the end of the decade.
Development Roadmap of Semiconductor Encapsulating Material
Development Roadmap of Semiconductor Encapsulating Material (Part 2)
Future Plastic PGA Technology
New materials, new component designs, and continuous process improvements define the direction of plastic packaging improvements in Japan. Oki's roadmap for planned TSOP improvements in memory packaging for DRAMS, as shown in Table 4.5, is typical of plastic packaging roadmaps followed by Japan's consumer electronics industries: it shows reductions in package mounting and wire loop profile heights, reductions in leadframe thicknesses, and new materials to achieve improved reliability.
Memory Package (TSOP) Technology Roadmap
Table 4.6 shows a roadmap for logic ICs. It illustrates planned QFP, C-PGA, and TTQFP (thin-thin quad flat pack) developments. Future packages are expected to use 0.3 mm pin pitch for QFPs, 1.27 mm pitch for C-PGAs with 1000 I/Os, and 0.3 mm heights on TTQFPs.
Logic LSI Package Roadmap
In a potentially very significant development, Fujitsu in 1994 introduced bump integration technology (BIT) for flip chip applications. BIT allows 0.12 mm bump pitch with pin counts between 300 and 600 on 200 sq. mm to 500 sq. mm areas. Equal sized BGA packages would have fewer than 200 pins.