JAPAN'S ELECTRONIC PACKAGING STRATEGIES

As Figure 4.2 shows, Japan's competitive edge over the United States in electronic packaging derives from the breadth of its packaging expertise. There are few areas in which Japan lags the United States. In fact, Japan is covering all its bases by investing in packaging technologies that are required to protect existing markets and in new technologies to grow next-generation electronics markets. The Japanese electronics industry has invested heavily in the full range of packaging technologies, including plastic and ceramic packages, passive components, printed wiring board (PWB), and surface mount technologies (SMT). To keep costs down, Japan continues to stress the incremental development of packaging technologies for mass production, as shown in Figure 4.3.


Figure 4.2. Japanese competitive advantage from breadth of technology.


Figure 4.3. Mass production strategy for low-cost electronic products.

The JTEC panel's research suggests that Japanese firms will continue to push the miniaturization of electronic packaging technologies. Plastic packaging technologies will continue to evolve low-cost quad flat packs (QFP) into thinner and smaller-profile packages such as thin quad flat packs (TQFP) and tape-automated bonding (TAB) packages. The high-volume applications of discrete components are expected to continue to shrink in size from the current 1.0 x 0.5 mm to 0.8 x 0.4 mm built-in multichip packages of capacitors, resistors, and inductors. Printed wiring boards will also reduce line and via widths from the current 100 microns and 250 microns, respectively, to 50 microns. The current six-to-eight-layer boards are expected to average eight layers. All these technologies are expected to continue to be applied to surface mount applications. The current limit of 0.4 mm pitch in SMT applications is expected to reach 0.15 mm pitch by the turn of the century.

For nearly a decade, the camcorder has driven packaging technology developments for miniaturization, reduced weight, and digitization. As shown in Figure 4.4, this has driven IC packaging to fine-pitch and thin packages while pushing the exploitation of multichip modules. Since the early 1990s, cellular telephones have added pressure for miniaturization through increased functional integration. Today, personal computers are adding pressure for higher speed and multiple functions. The result is a push for development of new heat-dissipation solutions and for development of vertical packages. Japan's continued economic success is expected to rely on its ability to maintain leadership in a broad range of packaging technologies to achieve competitive cost reductions for future "personal electronic" units.


Figure 4.4. Electronic packaging trends (Matsushita Electric Co., Inc.).

The trend towards finer pin pitch creates a number of issues that must be addressed. For example, open leads and solder bridging must be prevented. The corresponding size of solder balls must also be reduced. Thin, small-outline packages (TSOP) require improved resins and filler materials to reduce cracking during IR reflow. New designs for heat dissipation include the addition of heat-sinks under the die. Package miniaturization requires further developments in high-density board assembly.


Published: February 1995; WTEC Hyper-Librarian