Discussions with large vertically integrated companies such as Hitachi and NEC reveal a belief that the practical economic limit to QFP packages is 0.3 mm, beyond which other technologies will be cheaper and higher in quality and performance. The driving force behind the QFP lies in the facts that this package can be thinned by almost 4 times and that the mounting height can be one of the lowest of any packages in the industry except TAB. In addition, this is the lowest cost single-chip package in the industry.
Figures 4.34 and 4.35 compare the package weight and mounting height on PWB for a number of packages as a function of pin count. Only TAB and TSOP, besides QFP, can meet future competitive requirements for thinness and light weight in packages.
Figure 4.34. Package weight versus pin count.
Figure 4.35. Lead pitch and mounting height.
As shown in Figure 4.36, Hitachi has selected QFP, TAB, and PGA as strategic packages. There is general agreement that the best alternative to QFP in low-pin-count consumer products and high-pin-count computer products will be BGA (ball grid array) or surface mount PGA (pin grid array). Japan sees BGA as a high-speed, high-pin-count package that also provides a compact solution. Figure 4.37 shows how BGA provides a smaller footprint at 1 mm pitch than the ultimate 0.15 mm-pitch QFP beyond 600 I/Os.
Figure 4.36. High pin count packages (Hitachi).
Figure 4.37. Relative package areas:
BGA versus QFP.
In contrast to the inspection needs of fine-pitch QFP, manufacturers like Hitachi do not believe there is a need to inspect the BGA joint, even though X-ray inspection may be possible. This is so because of the large pitch the area BGA provides. Hitachi also claims great flexibility in circuit design using BGAs, allowing V(sub)cc and V(sub)dd connection everywhere in addition to providing power and ground for each group of output buffers, reducing the simultaneous switching noise. The QFP approach does not provide this flexibility.
In parallel to surface mount options, Japanese industry is pursuing PGA options both in ceramics and plastics. Toshiba, for example, is already pursuing an 820-pin ceramic PGA on a 60 mm square ceramic substrate. The pin-grid pitch in this package is 1.27 mm (50 mils). Toshiba chose TAB connection to the 20 mm size chip using gang inner lead bonding and single-point outer lead bonding. The plastic PGA trend providing in excess of 2000 I/Os is discussed above in the plastic package section.
Figure 4.38 summarizes the overall Japanese packaging assembly trend, illustrating thin quad flat pack (TQFP) as its main thrust, with TAB and PGA as parallel thrusts. The BGA is expected in applications requiring over 400-600 I/Os. Beyond the miniaturization of QFP technologies, Japanese firms continue to develop chip on board, tape automated bonding, and flip chip technologies to meet increasing packaging density future requirements, as shown in Figure 4.39.
Figure 4.38. Japanese high pin count strategy (Oki).
Figure 4.39. Japanese packaging assembly strategy (Sharp).