As we indicated earlier, amorphous silicon thin-film transistors are the dominant active matrix technology, and most of the production investments have been made in amorphous silicon. Some Japanese companies are pursuing other technologies. The two others worthy of note are MIM and polysilicon thin-film transistor active matrix technology. Specifically, Toshiba and Seiko-Epson are pursuing MIM technology for large display applications, and Seiko-Epson and Sony are pursuing polysilicon technology for small display applications. We will review the MIM technology here and will discuss the polysilicon technology later in this chapter.
Amorphous silicon is the current technology of choice for most Japanese companies because it has adequate performance as an active matrix for current TV and all current computer applications; it is produced using a low-temperature process; and it is produced using a relatively simple process requiring equipment of modest cost.
The amorphous silicon thin-film transistor fabrication process is extremely simple. It can require as few as two mask steps, although most processes require about five mask levels. Figure 5.14 shows diagrammatically how amorphous silicon thin-film transistors are fabricated.
Figure 5.14. Amorphous Silicon Active Matrix Fabrication Process
As can be seen, most of the processes are readily scaled to large areas. The Plasma Enhanced Chemical Vapor Deposition (PECVD) process has been developed in the production of the amorphous silicon solar cells used in calculators and remote power sources. The large-area metal depositions have been developed through sputtering of high-quality coatings for CD discs and magnetic hard discs. Wet etching is a mature process, but specialized photolithography has been developed specifically for AMLCDs by experienced Very Large Scale Integration (VLSI) equipment manufacturers.
One of the problems common to TFT active matrices relates to the gate delays caused by the select line resistivity. These lines form resistance-capacitance transmission lines that delay and distort the gate pulses. These effects limit the ultimate size of an active matrix display. Kato et al. discussed this relationship, as depicted graphically in Figure 5.15. Typically, a-Si TFT fabrication processes have used high-resistivity thin refractory metals, which have exacerbated the resistivity problem. To demonstrate larger area displays, new metallization systems have been developed. These have included a number of bimetal systems, such as Mo-Ta (Dohjo, 1988; Moriyama, 1989; Ichikawa, 1989), W-Ta (Japan Display Digest, 1989), Ta-Al-Ta (Katayama, 1989), Cr-Al (Moriyama, 1990) and Ta-Cu-Ta (Ikeda, 1989).
Advances pertaining to commercialization are frequently not published. Critical advances relate to product/process yields. At this stage in their development, a-Si device yields are low enough that developers are exploring techniques for redundancy. Examples of these have been published by Nippon Telephone and Telegraph (NTT) (Nakajima, 1989) and Seiko-Epson (Matsueda, 1989). Other yield-enhancing techniques include isolation of conducting layers by insulators (Moriyama, 1989) and the use of triple-stacked insulators (Ichikawa, 1989) of TaOx/SiOx/SiNx.
NTT sought a commercial partner to co-develop two 15-inch diagonal flat-panel displays that could be used as a component of a high-resolution teleconferencing system with graphics and realistic video capabilities. NTT provided three specific technologies: redundancy technology, high-speed driver technology, and low- resistance bus-line technology.
Figure 5.15. Size Limitation of an Active Matrix Display
The display has a 4-bit gray scale and was developed in two versions. One, a VGA version, has 1920 x 480 TFT subpixels arranged in a stripe configuration for 640 x 480 color pixels. The second, a high-resolution version, has 1920 x 1600 TFT subpixels arranged into triads for 1280 x 800 color pixels. There are several driving modes for this display: 1120 x 750 color pixels at 40 frames per second interlaced; 640 x 400 color pixels at 56.4 frames per second progressive scan; and 1024 x 760 pixels (reference NTT trip report in Appendix B)!#flag.
One significant advance demonstrated by Hosiden is the amorphous silicon active matrix implementation of 10-inch diagonal full-color active matrix LCD using a halftone-gray scale method. This technique results in dramatic improvements in viewing angle by replacing each pixel with a number of subpixels. At any particular analog voltage, some of the subpixels may be operated in saturation thereby providing the wide viewing angle properties of a binary display in its contribution to the pixel transmission. As an example, the vertical viewing angle for a conventional display at 50% graylevel is -40 degrees, +12 degrees while the halftone gray scale is -65 degrees, +30 degrees.
Companies continue to develop MIM technology because it has adequate performance as an active matrix for personal (small-size) TV and monochrome and limited color computer applications; it is produced using a very-low-temperature process; and it can be produced using a very simple process requiring mostly low- cost equipment.
MIM Performance. The basic issue with MIM active matrix technology is the limited nonlinearity of the basic MIM devices. This problem is compounded by a strong temperature sensitivity. Furthermore the basic problem with all series diode-type active matrices is that device nonuniformities are directly translated into visual nonuniformities in gray scale. Most display manufacturers do not believe that MIMs offer sufficient cost advantages to offset their performance disadvantages. Toshiba and Seiko-Epson are the exceptions.
Toshiba has developed and demonstrated a commercial monochrome display using the MIM technology. Toshiba refers to this as TFD (thin-film diode) technology. The product, announced in 1991, is a 12-inch diagonal with 1052 x 900 pixels. It is expected that this product will be used by Toshiba in a SPARC workstation product and by Sun Microsystems.
Seiko-Epson currently markets 3- to 4-inch color TVs using MIM technology and expects to expand its production capacity to produce 10-inch diagonal and larger MIMs for the computer markets. Nonetheless, Seiko-Epson representatives expressed the need for continuing research in MIMs to extend the operating temperature range and increase the intrinsic nonlinearity, which is necessary for increasing the resolution gray scale capability of MIM displays. Current Seiko- Epson products are typically 3.5 inches diagonal with 220 x 300 pixels, stripe filter, and 32 levels of gray scale.
MIM Process Temperature Impact. MIM process temperatures are below 300 degrees centigrade. Thus MIMs can be fabricated on very low-cost glass substrates such as soda lime glasses or Nippon Electric Glass Company BLC glass. These glasses are potentially an order of magnitude less costly than the commonly used Corning 7059 glass.
MIM Process. The MIM fabrication process is extremely simple, requiring only two mask steps and very simple photolithography. Figure 5.16 shows diagrammatically how MIMs are fabricated.
Toshiba is aggressively working to develop very low-cost, high-throughput MIM production technology. As an example, it is using a proximity printer and soda lime glass dip-coated in SiO(subscript 2.)
Figure 5.16. MIM Fabrication