A large infrastructure of AMLCD equipment suppliers is being established in Japan. A summary of the principal suppliers is shown in Table 3.5.
In-line vertical two-sided deposition systems are used to deposit a-Si and the gate dielectric insulation layer (SiN or SiO2). Anelva, with over 80% of the world market, dominates this business. In-line deposition systems have multiple vacuum chambers connected via gate valves. Substrates are loaded in the window- frame-like trays that hold up to four substrates and are clamped against the substrate holder. The vertically-held substrates are transported into vacuum chambers. The first one or two chambers contain quartz heater lamps to elevate the substrate temperature to 300-350 degrees centigrade. Several deposition chambers follow the heater chamber, as shown in the schematic of Figure 3.5. SiN, a-Si and SiN, or N + a-Si are deposited consecutively in the process chambers. The first SiN layer is deposited in a NH3/SiH4 plasma with the substrates held at 300-350 degrees centigrade. The lower deposition temperature of the a-Si layer necessitates the incorporation of a cooling chamber in order to maintain a short tact time (10 minutes). A cross-section of the deposition chamber is shown in Figure 3.6. The voltage is applied to maintain the plasma. The substrate holder straddles a heater to maintain the elevated substrate deposition temperature.
Major Equipment Suppliers
Figure 3.5. ILV-9300 P-CVD System
The following list summarizes the capabilities of the Anelva 8-chamber CVD system:
After deposition, the substrates exit the unloading chamber and return to the front end of the chamber through a clean tunnel. The substrates stay in the tunnel for 30-60 minutes to cool. The PECVD system is normally situated in a service chase, with the load station and unloading platform of the tray protruding into the clean room.
Automated loading, particle levels, and downtime require considerable improvement.
Figure 3.6. Vertical Double-Sided Deposition Chamber
Horizonal transport sputtering systems are commonly used for data and scan metal lines as well as ITO. A typical ITO deposition system is shown in Figure 3.7. Very large systems containing many substrates can be deposited simultaneously. Chamber cleaning in sputtering systems, target exchange, and cryo-pump regeneration are the most time-consuming maintenance factors. A comparison of the factors that affect tact time in sputtering and PECVD is shown in Table 3.6.
Figure 3.7. Sputtering System
In a multimask process, photolithography productivity is critical. The two major Japanese mask aligner vendors, Nikon and Canon, have developed large-area aligners that are essentially derivatives of their IC exposure systems.
Nikon developed a 1:1 stepper capable of expensive large substrates using a step- and-repeat system. It utilizes standard 6-inch reticles and a stitching accuracy of 1.5 śm or better. The stitching accuracy is particularly important because significant errors can lead to grey scale shift across the stitching boundary, which can be quite visible. Several different masks are needed to produce the required patterns across the substrate. The reticle change time, exposure time, and substrate movement and alignment time all contribute to the throughput of the system. Nikon is at present the dominant vendor for large-area photolithography systems.
Factors Which Determine the Tact Time
Canon has developed a 1:1 mirror projection system in which a slit scans and exposes the photo mask and substrate. Large masks enable a large slit width, which produces a single exposure for a VGA display and avoids the issues of stitching. Because 10-inch panels need no reticle change, this technique has potentially high throughput, but mask costs are extremely high. This stepper is not yet widely used and does not yet appear to be performing as expected.
The MRS Stepper sold in Japan by DaiNippon Screen is now under evaluation in various companies. It is a 2:1 stepper that achieves high throughput by exposing two images at once through double-barrel optics. It has impressive built-in metrology and very user-friendly software. The magnification can be varied to compensate for substrate shrinkage. This system performs well; it is imported from the United States.
The critical challenges for photolithography are to further improve throughput while increasing stitching and alignment accuracy to satisfy future requirements for high- resolution displays. One possible approach to increase throughput is to use a large- area proximity aligner for noncritical layers. However, mixing and matching of proximity and stepper aligners has many issues. Proximity aligners could be successfully used for color-filter fabrication.
The Giant Technology Corporation is developing a printing technology for pattern formation. This is an interesting approach, but is still in its infancy.
Cleaning processes are one of the key factors in achieving higher yield. Around 80% of the defects come from particles on the substrate, which are almost impossible to completely eliminate. Cleaning prior to deposition and resist coating is very important. Particles greater than 1 śm are more important to remove than submicron particles. The importance of the cleaning methods at each step of the TFT process is described in Table 3.7. The key cleaning processes in the LCD process occur prior to polyimide alignment film coating and after rubbing the film. As freon cleaning is being phased out, alternative cleaning processes are being sought.
Importance of Cleaning at Each Step
The cleaning methods and processes are summarized in Tables 3.8 and 3.9. For cleaning particles larger than 2 microns, 70% are removed by brushing with the aid of a surfactant and low-pressure water spray to avoid damage. Roller-brush cleaning has the problem of leaving 100-300 particles on the back side of the substrate 5-7 mm from the edge. Disk brushing has recently proved to be superior, leaving fewer than 30 particles on the back side of the substrate. At present, during cleaning the substrate is often held around the edge. However, as the substrates become larger and possibly thinner (0.7 mm), they will need to be supported in the middle; this factor will cause further cleaning problems. The Megasonic method, which combines cleaning spray with ultrasonic energy, removes 90% of particles down to 0.3 śm and cleans off the surfactant. The various features of cleaning techniques are summarized in Table 3.10. Substrate charging problems have been associated with jet spraying equipment.
Cleaning Processes Used for TFT LCD
Cleaning Process and Method
Cleaning Techniques and Features
A typical spray process line is shown in Figure 3.8. Spinning is the dominant technique used to deposit photoresist. With a spinner incorporating a proximity plate above the substrate, 4% resist uniformity can be achieved. Efficient resist usage is important for cost reasons: 15-30 cc of resist per substrate is sufficient to obtain good uniformity. Another critical issue is throughput; at present, resist coating is achieved at a rate of 1 substrate per minute. A DaiNippon Screen process line is shown in Figure 3.9.
A complete cleaning, exposure, developing, and etching line is shown in Figure 3.10. Such complete lines are not used in manufacturing because the processes are not yet mature and need further development. DaiNippon Screen is the major supplier of wet processing equipment. A complete image photo process with AGV is shown in Figure 3.11.
Dry etching can provide much better line-width control, but, because it is a single- plate process, it is extremely slow. Considerable development is required to improve throughput for this process. Today's TFT labs require a very large number of dry etchers.
Various custom-built equipment has been developed, including space sprayers and rubbing machines for alignment layers.
Low-alkali-content Corning 7059 substrates, made by the fusion method, dominate AMLCD, with over 90% of the market. At present, the glass finishing process is as follows:
The fusion process produces a very high-quality finish that is, in principle, better than a polished surface. However, because the sheet is often damaged in the later finishing process, the substrates must be polished. In an effort to reduce cost, Corning developed a new process that preserves the fusion-quality finish, eliminating the necessity for polishing and the subsequent washing and inspection.
Figure 3.8. Process Line
Figure 3.9. Photo Process Line
Figure 3.10. Rinse/Wet Processing Line
Figure 3.11. General Image of Layout
The glass substrates are preshrunk by annealing and are slowly cooled to minimize dimensional changes during the temperature cycling of the TFT processes.
Table 3.11 summarizes the properties of available glass substrates. NEG OA2, Hoya NA40, and Corning 1733 are particularly interesting glasses with higher softening points than 7059, thus reducing shrinkage or maybe enabling the use of high- temperature processes such as low-temperature p-Si.
The establishing of a quality packaging technology is essential for AMLCD. As the resolution of the display increases, so does the need for low-cost higher density packaging. Table 3.12 and Figure 3.12 compare three types of packaging: chip-on-board, TAB, and chip-on-glass. At present, TAB, with an isotropic adhesive, is the mainstream approach for VGA AMLCD. The minimum pitch is 80-100 microns. Compact, thin LCD modules can be achieved because the TAB IC are positioned on the sides of the backlight.
Properties of Glass Substrate
Comparisons of Packaging Configuration
Figure 3.12. Packaging Configuration in LCDs
Chip-on-glass (COG) will be used in high-resolution projection LCDs; COG configurations are shown in Figure 3.13. The IC bonding methods are classified roughly into conductive rubber connection, metallic connection, and conductive resin adhesive. The COG technology that can assemble IC chips onto ITO terminal leads and also repair the inferior IC is strongly preferred.
Eight-level, 120-output-driver ICs have been developed at Sharp, NEC, and Hitachi. TI Japan and others are developing a 16-grey-level 192-output chip.
Figure 3.13. Various IC Bonding Methods