Site: GIANT TECHNOLOGY CORPORATION
AND HITACHI RESEARCH LABORATORY
Date Visited: October 2, 1991
Report Author: A. Firester
Chief Researcher, GTC-Director, Giant Electronics Research
Engineer, TFT display department
LCD Products Sales Engineering, Tokyo Office
Senior Researcher, Planning Office & The 9th
Senior Chief Engineer, Electron Tube Division
Our agenda for this meeting was as follows:
- Introduction (All)
- Review of Sarnoff p-Si (Firester)
- GTC (Kaneko and Nagae)
- LCD business issues (Odawara)
- Technical discussions (All)
This report follows the agenda above and covers items 3-5.
Giant Technology Corporation (GTC)
- GTC was organized for the period March 1989 to September 1994.
- 70% of the funding is provided by the Japan Key Technology Center. The
remaining 30% funding is provided by the member companies.
- Consists of 17 companies, including Thompson CSF and Hoechst.
- The goal is to develop basic technology for a 1-meter flat display.
- Funding was reduced to 2.8 billion yen for the 5.7-year period. The goal
was reduced to do only very basic research.
The GTC organization is shown below in Figure
Figure GTC.1. GTC Organization
Nagae provided results to date on the TFT printing process. (These results
will also be the subject of a paper at the IDRC).
- Goal is 1-minute cycle time with resolution of about 20 microns lines and
spaces. Use of step and repeat exposure is not possible for 1 meter. Throughput
vs. cost is too low.
- Actually achieved resolution of 3 microns features. Built polysilicon p-mos
TFTs with W/L = 19 microns/3 microns on 100 mm square glass substrates. Glass
used is Corning 7059 or Asahi AN. Also built shift register and invertor
- Process used is same as conventional Hitachi p-mos:
- Self-aligned gate
- Ion implantation
- Temperature < 600 degrees centigrade
- Mobility ÷40 cm2/v-sec
- Polysilicon is desired for peripheral integrated drive circuitry. For >
10" to 14" diagonal displays p-Si integrated drive circuitry is mandatory.
- Hitachi is still researching the problem of p-Si leakage current. Their
best results have been achieved on both silicon and glass substrates.
Reproducibility is inadequate for a production process.
- A much shorter process turn-around time is needed to accelerate the
development of p- Si.
- Hope to use Corning 7059 for a p-Si process below 550 degrees
- Basic process is not defined. Off current problem. Elimination of ion
implantation is desired.
- Hitachi strategy is to develop a p-Si process that has maximum commonality
with a-Si. Insertion strategy is to add special p-Si processes to existing a-Si
production line and run both p-Si and a-Si in parallel at first.
- Mobara production:
- Difficult to identify yield bottleneck
- Substrate is 200 mm x 270 mm
- One 10-inch diagonal display per substrate
- Use Canon MPT 2000 stepper
- Production of 10-inch color TFTs (for Hitachi Flora Laptop) is about
- Aluminum anodization equipment can handle a 20-inch panel
- A heat bias treatment is used in the process
- Dry etch silicon; wet etch Al and ITOM
- Dip-coat Corning 7059 in silica
- PECVD is very dirty; need better equipment
- ESD is a problem
- Two point defects/panel average
- Laser repair by cutting
- Experimenting with 1:1 holographic printing
- Mobara is producing few 5-inch and 6.3-inch displays. They concentrate on
10- inch because it is more profitable. Hitachi now buys.LCD driver ICs. They
prefer bigger displays because they use the same number of ICs per display.
- Line runs 24 hours/day, two shifts, about 250 people: 100/shift, and about
50 process engineers.
Published: June 1992; WTEC Hyper-